Datasheet > DS4000D0BGA

DS4000D0BGA

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
达拉斯 - DALLAS		/
页数	文件大小	规格书
14页	246K
描述
Oscillator, 10MHz Min, 19.44MHz Max, 13MHz Nom,

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数据手册

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DS4000D0BGA 数据手册

DS4000

Figure 1. DATA TRANSFER ON 2-WIRE SERIAL BUS

SDA

MSB

SLAVE

ADDRESS

3-5

R/W BIT

ACKNOWLEDGEMENT

SIGNAL FROM

RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM

RECEIVER

SCL

3-7

ACK

REPEATED IF

START

MORE BYTES ARE

TRANSFERRED

STOP CONDITION

CONDITION

OR REPEATED

START CONDITION

Data Transfer

Figures 2 and 3 detail how data transfer is accomplished on the 2-wire bus.

Depending on the R/ W bit in the transmission protocols as shown, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the

master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge

bit after each received byte. Data is transferred with the most significant bit (MSB) first.

2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte

(the slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes

transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes

other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The

master device generates all of the serial clock pulses and the START and STOP conditions. A transfer

is ended with a STOP condition or with a repeated START condition. Since a repeated START

condition is also the beginning of the next serial transfer, the bus is not released.

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