DS31415GN+

更新时间： 2024-01-29 11:42:13

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
5页	74K
描述
3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock

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数据手册

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DS31415GN+ 数据手册

ABRIDGED DATA SHEET

DS31415

Application Example

Typical Application Example, Traditional Frequency Synchronization

clock monitoring and selection,

hitless switching, holdover, phase

build-out, frequency conversion,

fractional scaling, jitter attenuation

19.44MHz, 38.88MHz,

25MHz, etc.

19.44MHz, 38.88MHz,

25MHz, etc.

OC1

OC1POS/NEG

IC1

IC2

system clocks to line cards

recovered line clocks

from system backplane,

SDH, SyncE, OTN, etc.

outputs from APLL: <1ps rms jitter,

OC2

DS31415

outputs from DFS: ~40ps rms jitter

OC2POS/NEG

MFSYNC

time alignment signal to line cards

(e.g. 1 PPS)

This diagram is just one example. MANY other applications are possible.

Typical Application Example, Frequency and Time Synchronization

Processor

packet data to/from central switch function

1588

Software

Local OSC

TCXO or

OCXO

SPI

DS31415

1588

Clock

system time, e.g. 1 PPS

system clock, e.g. 25MHz

other clocks

from port cards,

for SyncE or

1588+SyncE operation

line clocks, e.g. 25MHz

to all port cards

DPLL

123 4 5

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