ABRIDGED DATA SHEET
DS28EL22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
ELECTRICAL CHARACTERISTICS (continued)
(T = -40°C to +85°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SHA-256 ENGINE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Computation Current
Computation Time
I
t
mA
ms
CSHA
Refer to the full data sheet.
CSHA
Note 1: Limits are 100% production tested at T = +25°C and/or T = +85°C. Limits over the operating temperature range and rel-
A
A
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4: Typical value represents the internal parasite capacitance when V
is first applied. Once the parasite capacitance is
PUP
charged, it does not affect normal communication.
Note 5: Guaranteed by design and/or characterization only; not production tested.
Note 6: , V , and V are a function of the internal supply voltage, which is a function of V
V
, R
, 1-Wire timing, and
TL TH
HY
PUP PUP
capacitive loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values of
PUP
PUP
REC
V
, V , and V
.
TL TH
HY
Note 7: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 8: The voltage on IO must be less than or equal to V at all times when the master is driving IO to a logic-zero level.
ILMAX
Note 9: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 10: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V
to be detected as logic-zero.
TH
HY
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: Defines maximum possible bit rate. Equal to 1/(t
+ t
).
W0LMIN
RECMIN
Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15: Interval after t during which a bus master can read a logic 0 on IO if there is a DS28EL22 present. The power-up pres-
RSTL
ence detect pulse could be outside this interval. See the Typical Operating Characteristics for details.
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V to V . The actual
IL
TH
maximum duration for the master to pull the line low is t
+ t - ε and t
+ t - ε, respectively.
W1LMAX
F
W0LMAX F
Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V to the input-high
IL
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
+ t .
RLMAX
F
Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO dur-
ing the programming and computation interval should be such that the voltage at IO is greater than or equal to V
.
PUPMIN
A low-impedence bypass of R
requirement.
activated during programming and computation is the recommended way to meet this
PUP
Note 19: Refer to the full data sheet.
Note 20: Refer to the full data sheet.
Note 21: Write-cycle endurance is tested in compliance with JESD47G.
Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 23: Data retention is tested in compliance with JESD47G.
Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 25: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.
Maxim Integrated
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