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DS26514_11 PDF预览

DS26514_11

更新时间: 2022-10-27 16:32:05
品牌 Logo 应用领域
美信 - MAXIM 电阻器
页数 文件大小 规格书
305页 2670K
描述
4-Port T1/E1/J1 Transceiver Fully Internal Impedance Match, No External Resistor

DS26514_11 数据手册

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DS26514 4-Port T1/E1/J1 Transceiver  
LIST OF TABLES  
Table 4-1. T1-Related Telecommunications Specifications................................................................................... 14  
Table 4-2. E1-Related Telecommunications Specifications................................................................................... 15  
Table 5-1. Time Slot Numbering Schemes........................................................................................................... 16  
Table 8-1. Detailed Pin Descriptions .................................................................................................................... 20  
Table 9-1. CLKO Frequency Selection................................................................................................................. 32  
Table 9-2. Reset Functions.................................................................................................................................. 33  
Table 9-3. Registers Related to the Elastic Store ................................................................................................. 36  
Table 9-4. Elastic Store Delay After Initialization .................................................................................................. 37  
Table 9-5. Registers Related to the IBO Multiplexer ............................................................................................. 39  
Table 9-6. RSER Output Pin Definitions (GTCR1.GIBO = 0) ................................................................................ 43  
Table 9-7. RSIG Output Pin Definitions (GTCR1.GIBO = 0).................................................................................. 43  
Table 9-8. TSER Input Pin Definitions (GTCR1.GIBO = 0).................................................................................... 44  
Table 9-9. TSIG Input Pin Definitions (GTCR1.GIBO = 0)..................................................................................... 44  
Table 9-10. RSYNC Input Pin Definitions (GTCR1.GIBO = 0)............................................................................... 45  
Table 9-11. D4 Framing Mode ............................................................................................................................. 48  
Table 9-12. ESF Framing Mode........................................................................................................................... 49  
Table 9-13. SLC-96 Framing................................................................................................................................ 49  
Table 9-14. E1 FAS/NFAS Framing ..................................................................................................................... 51  
Table 9-15. Registers Related to Setting Up the Framer....................................................................................... 52  
Table 9-16. Registers Related to the Transmit Synchronizer ................................................................................ 53  
Table 9-17. Registers Related to Signaling........................................................................................................... 54  
Table 9-18. Registers Related to SLC-96............................................................................................................. 57  
Table 9-19. Registers Related to T1 Transmit BOC.............................................................................................. 59  
Table 9-20. Registers Related to T1 Receive BOC............................................................................................... 59  
Table 9-21. Registers Related to T1 Transmit FDL............................................................................................... 60  
Table 9-22. Registers Related to T1 Receive FDL................................................................................................ 60  
Table 9-23. Registers Related to E1 Data Link..................................................................................................... 61  
Table 9-24. Registers Related to Maintenance and Alarms .................................................................................. 63  
Table 9-25. T1 Alarm Criteria............................................................................................................................... 65  
Table 9-26. Registers Related to Transmit RAI (Yellow Alarm)............................................................................. 65  
Table 9-27. Registers Related to Receive RAI (Yellow Alarm).............................................................................. 66  
Table 9-28. T1 Line Code Violation Counting Options .......................................................................................... 67  
Table 9-29. E1 Line Code Violation Counting Options.......................................................................................... 67  
Table 9-30. T1 Path Code Violation Counting Arrangements................................................................................ 68  
Table 9-31. T1 Frames Out of Sync Counting Arrangements................................................................................ 68  
Table 9-32. Registers Related to DS0 Monitoring................................................................................................. 69  
Table 9-33. Registers Related to T1 In-Band Loop Code Generator..................................................................... 71  
Table 9-34. Registers Related to T1 In-Band Loop Code Detection...................................................................... 72  
Table 9-35. Register Related to Framer Payload Loopbacks ................................................................................ 73  
Table 9-36. HDLC-64/HDLC-256 Controller Features........................................................................................... 74  
Table 9-37. Registers Related to the HDLC-64..................................................................................................... 74  
Table 9-38. Recommended Supply Decoupling.................................................................................................... 84  
Table 9-39. Registers Related to Control of the LIU.............................................................................................. 87  
Table 9-40. Telecommunications Specification Compliance for DS26514 Transmitters......................................... 88  
Table 9-41. Transformer Specifications................................................................................................................ 88  
Table 9-42. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications ........................................................... 94  
Table 9-43. Jitter Attenuator Standards Compliance............................................................................................. 96  
Table 9-44. Registers Related to Configure, Control, and Status of BERT.......................................................... 100  
Table 10-1. Register Address Ranges (in Hex)................................................................................................... 102  
19-5856; Rev 4; 5/11  
7 of 305  

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