Datasheet > DS2465P+T

DS2465P+T

更新时间： 2022-03-03 21:49:59

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
31页	2053K
描述
SHA-256 Coprocessor with 1-Wire Master Function

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DS2465P+T 数据手册

ABRIDGED DATA SHEET

DS2465

SHA-256 Coprocessor with 1-Wire Master Function

1-Wire PORT

CONFIGURATION

AND TIMING

REGISTERS

T-TIME OSCILLATOR

I C

SDA

SCL

LINE

TRANSCEIVER

INTERFACE

CONTROLLER

SLPZ

GND

1-Wire MASTER

STATUS REGISTER

1-WIRE READ

DATA REGISTER

SCRATCHPAD

Refer to the full data sheet for this

information.

DS2465

USER EEPROM

PAGES

Refer to the full

data sheet.

Figure 1. Block Diagram

volatile. It contains factory-programmed device identi-

fication data, a personality byte, and the user memory

pages.

Memory

Figure 2 shows the memory organization of the DS2465.

The memory begins at address 00h with the input

scratchpad. The register section follows at address 60h.

Addresses 00 to 6F

Refer to the full data sheet for this information.

are implemented as

volatile SRAM. The 1-Wire port configuration settings

have default values that are loaded automatically during

power-on. The address range 70h and higher is non-

�� Maxim Integrated Products

1...3 4 567 8 9...31

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