Datasheet > 微控制器和处理器 > 其他 uPs/uCs/外围集成电路> DS2460S+T&R

DS2460S+T&R

更新时间： 2024-01-27 00:29:41

品牌	Logo	应用领域
美信 - MAXIM		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
9页	211K
描述
Microprocessor Circuit, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8

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DS2460S+T&R 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	Factory Lead Time：	6 weeks
风险等级：	1.3	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3/5 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	Other Microprocessor ICs
最大压摆率：	0.5 mA	最大供电电压：	5.5 V
最小供电电压：	2.7 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

DS2460S+T&R 数据手册

Abridged Data Sheet

DS2460

Slave Address

The slave address to which the DS2460 responds is shown in Figure 5. The logic states at the address pins AD0,

AD1 and AD2 determine the value of the address bits A0, A2, and A4. The address pins allow the device to

respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The

last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will

flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access

mode).

Figure 4. I²C Protocol Overview

ACK

bit

ACK

bit

MS-bit

SDA

Slave Address

Acknowledgment

from Receiver

Repeated if more bytes

are transferred

SCL

ACK

STOP Condition

Repeated START

Condition

START

Condition

Idle

Figure 5. DS2460 Slave Address

7-Bit Slave Address

AD0 R/W

AD2

AD1

Most Signi-

ficant Bit

AD2, AD1, AD0

Pin States

Determines

Read or Write

I²C Definitions

The following terminology is commonly used to describe I²C data transfers. The timing references are defined in

Figure 6.

Bus Idle or Not Busy

Both, SDA and SCL, are inactive and in their logic HIGH states.

START Condition

To initiate communication with a slave, the master has to generate a START condition. A START condition is

defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. A valid slave address must be

sent by the master and acknowledged by the slave before subsequent START conditions are recognized.

STOP Condition

To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as

a change in state of SDA from LOW to HIGH while SCL remains HIGH. A valid slave address must be sent by the

master and acknowledged by the slave before subsequent STOP conditions are recognized.

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