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DS2460S+T&R PDF预览

DS2460S+T&R

更新时间: 2024-01-06 19:12:08
品牌 Logo 应用领域
美信 - MAXIM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
9页 211K
描述
Microprocessor Circuit, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8

DS2460S+T&R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:6 weeks
风险等级:1.3JESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Other Microprocessor ICs
最大压摆率:0.5 mA最大供电电压:5.5 V
最小供电电压:2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

DS2460S+T&R 数据手册

 浏览型号DS2460S+T&R的Datasheet PDF文件第1页浏览型号DS2460S+T&R的Datasheet PDF文件第2页浏览型号DS2460S+T&R的Datasheet PDF文件第4页浏览型号DS2460S+T&R的Datasheet PDF文件第5页浏览型号DS2460S+T&R的Datasheet PDF文件第6页浏览型号DS2460S+T&R的Datasheet PDF文件第7页 
Abridged Data Sheet  
DS2460  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Setup Time for a Repeated  
START Condition  
tSU:STA  
0.6  
µs  
Data Hold Time  
Data Setup Time  
tHD:DAT  
tSU:DAT  
tSU:STO  
(Notes 11, 12)  
(Note 13)  
0.9  
µs  
ns  
µs  
100  
0.6  
Setup Time for STOP Condition  
Bus Free Time Between a  
STOP and START Condition  
Capacitive Load for Each Bus  
Line  
tBUF  
CB  
1.3  
µs  
pF  
(Note 14)  
400  
Note 1:  
Note 2:  
Note 3:  
Note 4:  
Note 5:  
Specification at -40°C is guaranteed by design and characterization only and not production tested.  
Write-cycle endurance is degraded as TA increases.  
Not 100% production-tested; guaranteed by reliability monitor sampling.  
Data retention is degraded as TA increases.  
Guaranteed by 100% production test at elevated temperature for a shorter amount of time;  
equivalence of this production test to data sheet limit at operating temperature range is established by  
reliability testing.  
Note 6:  
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term  
storage at elevated temperatures is not recommended; the device can lose its write capability after 10  
years at +125°C or 40 years at +85°C.  
Note 7:  
Note 8:  
Note 9:  
Note 10:  
Note 11:  
All values are referred to VIHmin and VILmax levels.  
Applies to SDA, SCL, AD2, AD1, AD0.  
Guaranteed by simulation only, not production tested.  
I/O pins of the DS2460 do not obstruct the SDA and SCL lines if VCC is switched off.  
The DS2460 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL  
signal) to bridge the undefined region of the falling edge of SCL.  
Note 12:  
Note 13:  
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the  
SCL signal.  
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement  
tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW  
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must  
output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the  
standard-mode I²C-bus specification) before the SCL line is released.  
CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according  
to I²C-Bus Specification v2.1 are allowed.  
Note 14:  
PIN DESCRIPTION  
PIN  
NAME  
AD0  
AD1  
AD2  
GND  
NC  
FUNCTION  
1
2
3
4
I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave  
address of the device, see Figure 5.  
Ground Reference  
Not Connected  
5
6
7
8
SDA  
SCL  
VCC  
I²C Serial Data Input/Output; must be tied to VCC through a pullup resistor.  
I²C Serial Clock Input; must be tied to VCC through a pullup resistor.  
Power Supply Input  
OVERVIEW  
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the  
DS2460. The DS2460 communicates with a host processor through its I²C bus interface in standard-mode or in  
fast-mode. The logic state of three address pins determines the I²C slave address of the DS2460, allowing up to 8  
devices to operate on the same bus segment without requiring a hub. For more information (including Figure 2)  
refer to the full version of the data sheet.  
3 of 9  

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