DS2167/DS2168
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE
DESCRIPTION
1
RST
I
Reset. A high-low-high transition clears all internal registers and reset both algo-
rithms. The device should be reset on system power-up, and/or when changing
to/from hardware mode.
2
3
TM0
TM1
I
I
Test Modes 0 and 1. Tie to V for normal operation
SS
4
5
6
7
8
9
A0
A1
A2
A3
A4
A5
Address Select. A0=LSB; A5=MSB. Must match address/command word to en-
able serial port write.
10
SPS
I
I
Serial Port Select. Tie to V to select the serial port, to V to select the hard-
DD SS
ware mode.
11
MCLK
Master Clock. 10 MHz clock for ADPCM processing “engine”; may asynchronous
to SCLK, CLKX and CLKY.
12
13
14
VSS
XIN
–
I
Signal Ground. 0.0 volts
X Data In. Samples on falling edge of CLKX during selected timeslots.
CLKX
I
X Data Clock. Data clock for X side PCM interface; must be coherent and rising
edge aligned with FSX.
15
16
17
18
FSX
XOUT
SCLK
SDI
I
O
I
X Frame Sync. 8 KHz frame sync for X side PCM interface.
X Data Out. Updated on rising edge of CLKX during selected timeslots.
Serial Data Clock. Used to write serial port registers.
I
Serial Data In. Data for onboard control registers. Sampled on rising edge of
SCLK.
19
20
21
22
CS
I
O
I
Chip Select. Must be low to write the serial port.
YOUT
FSY
Y Data Out. Updated on rising edge of CLKY during selected timeslots.
Y Frame Sync. 8 KHz frame sync for Y side PCM interface.
CLKY
I
Y Data Clock. Data clock for Y side PCM interface; must be coherent and rising
edge aligned with FSY.
23
24
YIN
I
Y Data In. Samples on falling edge of CLKY during selected timeslots.
Positive Supply. 5.0 volts.
VDD
–
should also be asserted when changing to/from the
HARDWARE RESET
RST allows the user to reset both channel algorithms
and register contents. This input must be held low for at
least 1 ms on system power-up after master clock is
stable to assure proper initialization of the device. RST
hardware mode. RST clears all bits of the control regis-
ter except IPD; IPD is set for both channels, powering
down the device.
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