Datasheet > DS1831B/T&R

DS1831B/T&R

更新时间： 2024-02-01 16:47:43

品牌	Logo	应用领域
美信 - MAXIM		光电二极管
页数	文件大小	规格书
16页	253K
描述
Power Supply Support Circuit, Fixed, 4 Channel, PDIP16, 0.300 INCH, PLASTIC, DIP-16

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技术参数
数据手册

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DS1831B/T&R 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.29
Base Number Matches：	1

DS1831B/T&R 数据手册

DS1831/A/B

OUTPUT VALID CONDITIONS

The DS1831 can maintain valid outputs as long as one input remains above 1.0V. Accurate voltage

monitoring additionally requires that either the 3.3V IN or 5V IN input be above 1.5V. If this condition is

not met and at least one of the supply inputs are at or above 1.0V all outputs are maintained in the active

condition. The DS1831 requires pull-up resistors on the outputs to maintain a valid output. The value of

the pull up resistor is not critical in most cases but must be set low enough to pull the output to a high

state. A common pull-up resistor value used is 10kꢀ (see Figure 7).

APPLICATION DIAGRAM—OPEN DRAIN OUTPUTS Figure 7

3.3V Supply

5V Supply

IN_5V

IN_3.3v

10 kꢀ

10 K

ꢀ

RST_3.3V

RST_5V

DS1831

TOL_5V

TD_5V

TOL_3.3V

TD_3.3V

PBRST_5V

PBRST_3.3V

GND

NOTE: If outputs are at different voltages the outputs can not be connected to form a wired AND.

OPERATION—NON-MASKABLE INTERRUPT

The DS1831 has two referenced comparator (DS1831A has only one referenced comparator) that can be

used to monitor upstream voltages or other system specific voltages. Each comparator is referenced to the

1.25V internal band gap reference and controls an open-drain output. When a voltage being monitored

decays to the voltage sense point, the DS1831 pulses the NMI output to the active state for a minimum

10µs. The comparator detection circuitry also has built-in hysteresis of 100µV. The supply must be below

the voltage sense point for approximately 2µs before a low NMI will be generated. In this way, power

supply noise is minimized in the monitoring function, reducing false interrupts. See Figure 8 for the non-

maskable timing diagram.

Versatile trip voltages can be configured by the use of an external resistor divider to divide the voltage at

a sense point to the 1.25V trip levels of the referenced comparators. See Figure 9 for an example circuit

diagram and sample equations. The equations demonstrate a design process to determine the resistor

values to use.

Connecting one or both NMI outputs to one of the reset specific PBRST s allows the non-maskable

interrupt to generate an automatic reset for the reset time period when an out-of-tolerance condition

occurs in a monitored supply. An example is shown in Figure 9.

7 of 14

1...4 5 678 9 10...16

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