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DS1710S PDF预览

DS1710S

更新时间: 2024-01-08 12:45:20
品牌 Logo 应用领域
达拉斯 - DALLAS 微控制器和处理器外围集成电路uCs集成电路uPs集成电路光电二极管
页数 文件大小 规格书
14页 212K
描述
Microprocessor Circuit, CMOS, PDSO16, 0.300 INCH, SOIC-16

DS1710S 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.69
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

DS1710S 数据手册

 浏览型号DS1710S的Datasheet PDF文件第1页浏览型号DS1710S的Datasheet PDF文件第3页浏览型号DS1710S的Datasheet PDF文件第4页浏览型号DS1710S的Datasheet PDF文件第5页浏览型号DS1710S的Datasheet PDF文件第6页浏览型号DS1710S的Datasheet PDF文件第7页 
DS1710  
DESCRIPTION  
The DS1710 is a low-power CMOS circuit which solves the application problems of converting CMOS  
RAMS into nonvolatile memories. In addition the device has the ability to unconditionally write protect  
blocks of memory so that inadvertent write cycles do not corrupt program and special data space. The  
incoming power supply voltage at the VCCI input pin is constantly monitored for an out-of-tolerance  
condition. When such a condition is detected, both the chip enable and write enable outputs are inhibited  
to protect stored data. The battery inputs are used to supply VCCO with power when VCCI is less than the  
battery input voltages. Special circuitry uses a low leakage CMOS process which affords precise voltage  
detection at extremely low current consumption. By combining the DS1710 Partitioned NV Controller  
chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved.  
The DS1710 Partitioned NV Controller incorporates all the functions of the DS1610 with the additional  
feature of either +3.0V or +5.0V operation. The DS1710 functions like the Dallas Semiconductor DS1210  
NV controller when the ( DIS) disable pin is grounded and also incorporates the power-up auto sensing.  
An internal pulldown resistor to ground on the DIS pin of the DS1710S allows it to retrofit into DS1210S  
applications. When the DIS pin is grounded the address inputs AW - AZ and the write enable input WEI  
are ignored. Also the power-fail output PFO and the write enable output WEO are tristated.  
POWER-UP AUTO SENSING  
VCCI will accept either +3.0V or +5.0V input. Selection of 3V operation is automatically invoked when  
VCC rises and remains between VCCTP2 and VCCTP1 for tREC. 5V operation is automatically selected if VCC  
rises and remains above both VCCTP2 and VCCTP1 for tREC. In either case, tREC is measured from the time  
VCC first rises above VCCTP2. The DS1710 will not change modes until VCC falls below VCCTP2  
.
OPERATION - DISABLE PIN CONNECTED TO VCCO  
The DS1710 performs five circuit functions required to battery-backup a RAM. First, a switch is provided  
to direct power from the battery or the incoming power supply (VCCI) depending on which is greater. This  
switch has a voltage drop of less than 0.2 volts. The second function provided by the DS1710 is power-  
fail detection. The incoming supply (VCCI) is constantly monitored. When the supply goes out of  
tolerance a precision comparator detects power failure and inhibits both the chip enable output (CEO ) and  
the write enable output ( WEO ). A third function of write protection is accomplished by holding both the  
chip enable output CEO and write enable output WEO to within 0.2 volts of VCCO when VCCI is out of  
tolerance. If CEI is low at the time that power-fail detection occurs the CEO signal is kept low until CEI  
is brought high again. However, CEO is forced high after 1.5 µs regardless of the state of CEI . Similarly,  
if WEI is low at the time that power-fail detection occurs, the WEO signal will remain low until WEI is  
brought high or 1.5 µs elapses. The delay of write protection until the current memory cycle is complete  
prevents corrupted data. Power-fail detection occurs in the range of 4.75 to 4.5 volts with the tolerance  
pin TOL grounded and in 5-volt mode. If the tolerance pin is connected to VCCO while in 5-volt mode,  
then power-fail detection occurs in the range of 4.5 volts to 4.25 volts. If in 3-volt mode, the power-fail  
detection will occur in the range of 2.7 to 2.5 volts. The PF0 signal is driven low and remains low until  
VCCI returns to nominal conditions. During nominal supply conditions CEO will follow CEI and WEO  
will follow WEI . The fourth function which the DS1710 performs is a battery status warning so that  
potential data loss is avoided. Each time VCCI is applied to the device battery status is checked with a  
precision comparator. If during battery backup, no switch occurred from one battery to the other, the  
voltage of the battery supplying power when VCCI is applied is checked. If this voltage is less than 2.0  
volts the second chip enable cycle after power is applied is inhibited. If any switch from one battery to  
another did occur the voltage of both batteries is checked. If either voltage is less than 2.0 volts the  
second chip enable cycle will be inhibited. Battery status can therefore be determined by performing a  
2 of 14  

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