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DS16EV5110SQX/NOPB PDF预览

DS16EV5110SQX/NOPB

更新时间： 2024-02-17 06:26:58
品牌 Logo 应用领域
德州仪器 - TI 音频控制集成电路消费电路商用集成电路
页数 文件大小 规格书
24页 3233K
描述
用于 DVI、HDMI 接收器端应用的视频均衡器 (3D+C) | NJU | 48 | -40 to 85

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DS16EV5110SQX/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN, LCC48,.27SQ,20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.05商用集成电路类型：EQUALIZER CIRCUIT
JESD-30 代码：S-PQCC-N48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
信道数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Other Consumer ICs
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm

DS16EV5110SQX/NOPB 数据手册

 浏览型号DS16EV5110SQX/NOPB的Datasheet PDF文件第2页浏览型号DS16EV5110SQX/NOPB的Datasheet PDF文件第3页浏览型号DS16EV5110SQX/NOPB的Datasheet PDF文件第4页浏览型号DS16EV5110SQX/NOPB的Datasheet PDF文件第6页浏览型号DS16EV5110SQX/NOPB的Datasheet PDF文件第7页浏览型号DS16EV5110SQX/NOPB的Datasheet PDF文件第8页 
DS16EV5110  
www.ti.com  
SNLS249M –FEBRUARY 2007–REVISED APRIL 2013  
Electrical Characteristics (continued)  
Over recommended operating supply and temperature ranges unless other specified.(1)(2)  
Symbol  
Parameter  
Conditions  
DC to 50MHz  
Min  
Typ  
Max  
Units  
(3)  
N
Supply Noise Tolerance  
100  
mVP-P  
CML INPUTS  
VTX  
Input Voltage Swing (Launch  
Amplitude)  
Measured differentially at TPA  
(Figure 2)  
800  
1200  
mVP-P  
V
VICMDC  
VIN  
Input Common-Mode Voltage  
DC-Coupled Requirement  
Measured at TPA (Figure 2)  
VDD-0.3  
VDD-0.2  
Input Voltage Swing  
Measured differentially at TPB  
(Figure 2)  
120  
mVP-P  
RLI  
Differential Input Return Loss  
Input Resistance  
100 MHz– 825 MHz, with fixture's  
effect de-embedded  
10  
50  
dB  
RIN  
IN+ to VDD and IN− to VDD  
45  
55  
Ω
CML OUTPUTS  
VO  
Output Voltage Swing  
Measured differentially with OUT+  
and OUT− terminated by 50Ω to  
VDD  
800  
VDD-0.3  
75  
1200  
VDD-0.2  
240  
mVP-P  
V
VOCM  
tR, tF  
Output common-mode Voltage  
Transition Time  
Measured Single-ended  
20% to 80% of differential output  
voltage, measured within 1" from  
output pins.  
ps  
tCCSK  
Inter Pair Channel-to-Channel  
Skew (all 4 Channels)  
Difference in 50% crossing  
between shortest and longest  
channels  
25  
ps  
ps  
tD  
Latency  
350  
OUTPUT JITTER  
TJ1  
Total Jitter at 1.65 Gbps  
20m 28 AWG STP DVI Cable  
Data Paths  
0.13  
0.2  
0.17  
UIP-P  
EQ Setting 0x04 PRBS7(4) (5) (6)  
TJ2  
Total Jitter at 2.25 Gbps  
20m 28 AWG STP DVI Cable  
Data Paths  
UIP-P  
UIP-P  
EQ Setting 0x04 PRBS7(4) (5) (6)  
TJ3  
TJ4  
Total Jitter at 165 MHz  
Total Jitter at 225 MHz  
Random Jitter  
Clock Paths  
0.165  
Clock Pattern(4) (5) (6)  
Clock Paths  
0.165  
3
UIP-P  
psrms  
Clock Pattern(4) (5) (6)  
(6) (7)  
RJ  
See  
BIT RATE  
FCLK  
Clock Frequency  
Bit Rate  
Clock Path(4)  
Data Path(4)  
25  
225  
MHz  
BR  
0.25  
2.25  
Gbps  
(3) Allowed supply noise (mVP-P sine wave) under typical conditions.  
(4) Specification is ensured by characterization and is not tested in production.  
(5) Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of  
Figure 2). Random jitter is removed through the use of averaging or similar means.  
(6) Total Jitter is defined as peak-to-peak deterministic jitter from () + 14.2 times random jitter in psrms  
.
(7) Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in psrms, see  
TPC of Figure 2; JIN is the random jitter at the input of the equalizer in psrms, see TPA of Figure 2.  
Copyright © 2007–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: DS16EV5110  
 
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