Datasheet > DS1077LU-66.66

DS1077LU-66.66

更新时间： 2024-02-17 17:04:01

品牌	Logo	应用领域
达拉斯 - DALLAS		/
页数	文件大小	规格书
20页	277K
描述
Oscillator,

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技术参数
数据手册

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DS1077LU-66.66 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84	Base Number Matches：	1

DS1077LU-66.66 数据手册

DS1077L

TABLE 5

BIT VALUE

DIVISOR (N)

0 000 000 000*

0 0 00 0 00 001

—

1 111 111 111

*Default Condition

1025

BUS WORD

NAME

—

Factory Default

*These bits are reserved and must be set to zero.

A0, A1, A2

(Default Setting = 000)

(Default Setting WC = 0)

These are the device select bits that determine the address of the device.

This bit determines when/if the EEPROM is written to after register contents have been changed.

If WC = 0, the EEPROM is automatically written after a write register command.

If WC = 1, the EEPROM is only written when the WRITE command is issued.

Regardless of the value of the WC bit, the value of the BUS register (A0, A1, and A2) is always

immediately written to the EEPROM.

2-WIRE SERIAL DATA BUS

The DS1077L supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls

the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must

be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions. The DS1077L operates as a slave on the 2-wire bus.

Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pullup resistor (5k) is

connected to SDA.

The following bus protocol has been defined (see Figure 2):

C Data transfer may be initiated only when the bus is not busy.

C During data transfer, the data line must remain stable whenever the clock line is high. Changes in

the data line while the clock line is high will be interpreted as control signals.

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