TECHNICAL INFORꢀATION
DIGITAL INPUTS
TABLE 3ꢁ PINOUTS
FUNCTION PIN
PIN
FUNCTION
1
2
3
±
5
6
7
8
LL-B
19
20
21
22
23
2±
25
26
27
28
29
30
31
32
33
3±
35
36
Bit 16 (LSB)
Bit 15
Bit 1±
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit ±
Bit 3
Bit 2
Bit 1 (MSB)
LM-A
LM-B
COS A
SIN A
GC1-B
GC2-B
Ref B
GC1-A
GC2-A
Ref A
COS B
SIN B
NC
+15 V
-15 V
LA-B
LA-A
LL-A
For each channel, the 16-bit digital angle is double buffered with
transparent latches (See FIGURE 1). The latch controls have
internal pull-up current sources to +5 V, this puts the latches in
the transparent mode when they are not connected.
Angle is determined by adding the logic bits. The enable inputs
are LL (1st Latch LSBs), LM (1st Latch MSBs), and LA (2nd
Latch All); see FIGURE 2 for timing.
9
10
11
12
13
1±
15
16
17
18
OUTPUT SCALING AND REFERENCE LEVEL
ADJUSTꢀENT
The DRC-11522 operates like a multiplying D/A converter in that
the voltage of each output line is directly proportional to the ref-
erence voltage. The maꢀimum line-to-line levels are determined
by the output amplifiers and are programmable for a gain of 0.5,
1.0, or 2.0 (See TABLE 2.).
GND
NOTE: Functions LL, LM, LA both A and B may be left unconnected
when not used.
TABLE ±ꢁ PROGRAꢀꢀABLE GAIN
TABLE 4ꢁ PIN DEFINITIONS
GC1-A
(PIN 7)
GC±-A
GAIN
PIN
GND
DEFINITION
(PIN 8)
(K)
Power Supply Ground
Digital Ground
Analog Signal Ground
GND
OPEN
OPEN
OPEN
GND
OPEN
0.5
1.0
2.0
B1-B16
LM-A
Digital Input bits B1, = MSB = 180 degrees
High Byte Enable (B1-B8) for MSB’s 8-bit Input register of
channel A. Logic high enables, low holds.
High Byte Enable (B1-B8) for MSB’s 8-bit Input register
channel B Logic high enables, low holds.
Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of
channel A. Logic high enables, low holds
Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of
channel B. Logic high enables, low holds.
Channel A Load Converter. Logic high transfers Channel A
input registers data into 16-bit holding register. When
low, Channel A is in hold mode.
Channel B Load Converter. Logic high transfers Channel B
input registers data into 16-bit holding register. When
low, Channel B is in hold mode.
Power Supply Voltage.
Power Supply Voltage.
GC1-B
(PIN ±)
GC±-B
GAIN
(PIN 5)
(K)
LM-B
LL-A
LL-B
LA-A
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
sin = (REF * K) A [1 + A(θ)] sin θ
o
cos = (REF * K) A [1 + A(θ)] cos θ
o
LA-B
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (REF * K). The
+15 V
-15 V
transformation ratio A is determined by the programmable gain
o
CAUTION:
REVERSAL OF POWER SUPPLIES
WILL DAꢀAGE THE CONVERTERꢁ
Channel A reference voltage Input
Channel B reference voltage input
Channel A gain programming pin
Channel A gain programming pin
Channel B gain programming pin
Channel B gain programming pin
Analog output of Channel A
inputs (0.5, 1.0, or 2.0). The maꢀimum variation in A from all
o
causes is 0.1%. The term A(θ) represents the variation of the
amplitude with the digital signal input angle. A(θ), which is called
the scale factor variation, is a smooth function of (θ) without dis-
continuities and is less than ±0.1% for all values of (θ) The total
Ref-A
Ref-B
GC1-A
GC2-A
GC1-B
GC2-B
Sin A
Cos A
Sin B
Cos B
maꢀimum variation in A [1 + A(θ)] is therefore ±0.2%.
o
Because the amplitude factor (REF * K) A [1 + A(θ)] varies
o
Analog output of Channel A
Analog output of Channel B
Analog output of Channel B
simultaneously on all output lines, it is not a source of error when
the DRC-11522 is driving a ratiometric system. However, if the
outputs are used independently, as in ꢀ-y plotters, the amplitude
variations must be taken into account.
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