May 1989
DP8409A Multi-Mode Dynamic RAM Controller/Driver
General Description
Operational Features
Y
All DRAM drive functions on one chipÐminimizes skew
on outputs, maximizes AC peformance
On-chip capacitive-load drives (specified to drive up to
88 DRAMs)
Dynamic memory system designs, which formerly required
several support chips to drive the memory array, can now
be implemented with a single IC . . . the DP8409A Multi-
Mode Dynamic RAM Controller/Driver. The DP8409A is ca-
pable of driving all 16k and 64k Dynamic RAMs (DRAMs) as
well as 256k DRAMs. Since the DP8409A is a one-chip so-
lution (including capacitive-load drivers), it minimizes propa-
gation delay skews, the major performance disadvantage of
multiple-chip memory drive and control.
Y
Y
Y
Y
Y
Drives directly all 16k, 64k, and 256k DRAMs
Capable of addressing 64k, 256k, or 1M words
Propagation delays of 25 ns typical at 500 pF load
CAS goes low automatically after column addresses are
valid if desired
The DP8409A’s 8 modes of operation offer a wide selection
of DRAM control capabilities. Memory access may be con-
trolled externally or on-chip automatically; an on-chip re-
fresh counter makes refreshing (either externally or auto-
matically controlled) less complicated; and automatic mem-
ory initialization is both simple and fast.
Y
Y
Y
Y
Auto Access mode provides RAS, row to column se-
lect, then CAS automatically and fast
WE follows WIN unconditionallyÐoffering READ,
WRITE or READ-MODIFY-WRITE cycles
On-chip 9-bit refresh counter with selectable End-of-
Count (127, 255 or 511)
The DP8409A is a 48-pin DRAM Controller/Driver with 9
multiplexed address outputs and 6 control signals. It con-
sists of two 9-bit address latches, a 9-bit refresh counter,
and control logic. All output drivers are capable of driving
500 pF loads with propagation delays of 25 ns. The
DP8409A timing parameters are specified driving the typical
load capacitance of 88 DRAMs, including trace capaci-
tance.
End-of-Count indicated by RF I/O pin going low at 127,
255 or 511
Y
Y
Y
Low input on RF I/O resets 9-bit refresh counter
CAS inhibited during refresh cycle
Fall-through latches on address inputs controlled by
ADS
Y
Y
Y
TRI-STATE outputs allow multi-controller addressing of
memory
The DP8409A has 3 mode-control pins: M2, M1, and M0,
where M2 is in general REFRESH. These 3 pins select 8
modes of operation. Inputs B1 and B0 in the memory ac-
e
Control output signals go high-impedance logic ‘‘1’’
when disabled for memory sharing
Power-up: counter reset, control signals high, address
outputs TRI-STATE, and End-of-Count set to 127
cess modes (M2
1), are select inputs which select one of
four RAS outputs. During normal access, the 9 address out-
puts can be selected from the Row Address Latch or the
Column Address Latch. During refresh, the 9-bit on-chip re-
fresh counter is enabled onto the address bus and in this
mode all RAS outputs are selected, while CAS is inhibited.
Mode Features
Y
8 modes of operation: 3 access, 3 refresh, and 2
set-up
Y
The DP8409A can drive up to 4 banks of DRAMs, with each
bank comprised of 16k’s, 64k’s, or 256k’s. Control signal
outputs RAS, CAS, and WE are provided with the same
drive capability. Each RAS output drives one bank of
DRAMs so that the four RAS outputs are used to select the
banks, while CAS, WE, and the multiplexed addresses can
be connected to all of the banks of DRAMs. This leaves the
non-selected banks in the standby mode (less than one
tenth of the operating power) with the data outputs in TRI-
2 externally controlled modes: 1 access and 1 refresh
(Modes 0, 4)
Y
2 auto-access modes RAS
e
x
R/C
20 or 30 ns minimum (Modes 5, 6)
x
CAS automatic,
with t
RAH
Y
Y
Auto-access mode allows Hidden Refreshing (Mode 5)
Forced Refresh requested on RF I/O if no Hidden Re-
fresh (Mode 5)
Y
Y
Y
Y
Y
Forced Refresh performed after system acknowledge of
request (Mode 1)
STATE . Only the bank with its associated RAS low will be
É
written to or read from.
Automatic Burst Refresh mode stops at End-of-Count
of 127, 255, or 511 (Mode 2)
2 All-RAS Acces modes externally or automatically con-
trolled for memory initialization (Modes 3a, 3b)
Automatic All-RAS mode with external 8-bit counter
frees system for other set-up routines (Mode 3a)
End-of-Count value of Refresh Counter set by B1 and
B0 (Mode 7)
TL/F/8409–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
PALÉ is a registered trademark of and used under license with Monolithic Memories Inc.
C
1995 National Semiconductor Corporation
TL/F/8409
RRD-B30M105/Printed in U. S. A.
5秒后页面跳转
SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
AT89C51单片机资料手册详细解析及应用示例
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
