2.0 Block Diagram
TL/F/7405–2
FIGURE 1. DP8392A Block Diagram
3.0 Functional Description
The CTI consists of four main logical blocks:
Receiver then stays off only if within about 1 ms, the DC
level from the low pass filter rises above the DC squelch
threshold. Figure 2 illustrates the Receiver timing.
a) the Receiver - receives data from the coax and sends it
to the DTE
The differential line driver provides ECL compatible signals
to the DTE with typically 3 ns rise and fall times. In its idle
state, its outputs go to differential zero to prevent DC stand-
ing current in the isolation transformer.
b) the Transmitter - accepts data from the DTE and trans-
mits it onto the coax
c) the Collision Detect circuitry - indicates to the DTE any
collision on the coax
3.2 TRANSMITTER FUNCTIONS
d) the Jabber Timer - disables the Transmitter in case of
longer than legal length packets
The Transmitter has a differential input and an open collec-
tor output current driver. The differential input common
mode voltage is established by the CTI and should not be
altered by external circuitry. The transformer coupling of
g
TX will satisfy this condition. The driver meets all IEEE
802.3/Ethernet Specifications for signal levels. Controlled
3.1 RECEIVER FUNCTIONS
The Receiver includes an input buffer, a cable equalizer, a
4-pole Bessel low pass filter, a squelch circuit, and a differ-
ential line driver.
The buffer provides high input impedance and low input ca-
pacitance to minimize loading and reflections on the coax.
g
rise and fall times (25 ns V 5 ns) minimize the higher
harmonic components. The rise and fall times are matched
to minimize jitter. The drive current levels of the DP8392A
meet the tighter recommended limits of IEEE 802.3 and are
set by a built-in bandgap reference and an external 1% re-
sistor. An on chip isolation diode is provided to reduce the
Transmitter’s coax load capacitance. For Ethernet compati-
ble applications, an external isolation diode (see Figure 4 )
may be added to further reduce coax load capacitance. In
Cheapernet compatible applications the external diode is
not required as the coax capacitive loading specifications
are relaxed.
The equalizer is a high pass filter which compensates for
the low pass effect of the cable. The composite result of the
maximum length cable and the equalizer is a flatband re-
sponse at the signal frequencies to minimize jitter.
The 4-pole Bessel low pass filter extracts the average DC
level on the coax, which is used by both the Receiver
squelch and the collision detection circuits.
The Receiver squelch circuit prevents noise on the coax
from falsely triggering the Receiver in the absence of the
signal. At the beginning of the packet, the Receiver turns on
when the DC level from the low pass filter is lower than the
DC squelch threshold. However, at the end of the packet, a
quick Receiver turn off is needed to reject dribble bits. This
is accomplished by an AC timing circuit that reacts to high
level signals of greater than typically 200 ns in duration. The
The Transmitter squelch circuit rejects signals with pulse
widths less than typically 20 ns (negative going), or with
b
levels less than 175 mV. The Transmitter turns off at the
end of the packet if the signal stays higher than 175 mV
b
for more than approximately 300 ns. Figure 3 illustrates the
Transmitter timing.
2
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