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DP8392AN

更新时间： 2024-02-11 15:56:41
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口电信集成电路电信电路光电二极管以太网：16GBASE-T
页数 文件大小 规格书
10页 175K
描述
Coaxial Transceiver Interface

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DP8392AN 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8JESD-30 代码：S-PQCC-J28
长度：11.43 mm功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER认证状态：Not Qualified
座面最大高度：4.57 mm最大压摆率：180 mA
表面贴装：YES电信集成电路类型：ETHERNET TRANSCEIVER
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：11.43 mmBase Number Matches：1

DP8392AN 数据手册

 浏览型号DP8392AN的Datasheet PDF文件第2页浏览型号DP8392AN的Datasheet PDF文件第3页浏览型号DP8392AN的Datasheet PDF文件第4页浏览型号DP8392AN的Datasheet PDF文件第6页浏览型号DP8392AN的Datasheet PDF文件第7页浏览型号DP8392AN的Datasheet PDF文件第8页 
5.0 Pin Descriptions  
Pin No.  
Name  
I/O  
Description  
*
a
b
1
2
CD  
CD  
O
Collision Output. Balanced differential line driver outputs from the collision detect  
circuitry. The 10 MHz signal from the internal oscillator is transferred to these  
outputs in the event of collision, excessive transmission (jabber), or during CD  
Heartbeat condition. These outputs are open emitters; pulldown resistors to VEE  
are required. When operating into a 78X transmission line, these resistors should  
be 500X. In Cheapernet applications, where the 78X drop cable is not used,  
higher resistor values (up to 1.5k) may be used to save power.  
*
a
b
3
6
RX  
RX  
O
I
Receive Output. Balanced differential line driver outputs from the Receiver. These  
outputs also require 500X pulldown resistors.  
*
a
b
7
8
TX  
TX  
Transmit Input. Balanced differential line receiver inputs to the Transmitter. The  
common mode voltage for these inputs is determined internally and must not be  
externally established. Signals meeting Transmitter squelch requirements are  
waveshaped and output at TXO.  
9
HBE  
I
I
I
Heartbeat Enable. This input enables CD Heartbeat when grounded, disables it  
when connected to VEE.  
a
b
11  
12  
RR  
RR  
External Resistor. A fixed 1k 1% resistor connected between these pins  
establishes internal operating currents.  
14  
RXI  
Receive Input. Connects directly to the coaxial cable. Signals meeting Receiver  
squelch requirements are equalized for inter-symbol distortion, amplified, and  
g
outputted at RX  
.
15  
16  
TXO  
CDS  
O
I
Transmit Output. Connects either directly (Cheapernet) or via an isolation diode  
(Ethernet) to the coaxial cable.  
Collision Detect Sense. Ground sense connection for the collision detect circuit.  
This pin should be connected separately to the shield to avoid ground drops from  
altering the receive mode collision threshold.  
10  
GND  
VEE  
Positive Supply Pin. A 0.1 mF ceramic decoupling capacitor must be connected  
across GND and VEE as close to the device as possible.  
4
5
Negative Supply Pins. In order to make full use of the 3.5W power dissipation  
capability of this package, these pins should be connected to a large metal frame  
area on the PC board. Doing this will reduce the operating die temperature of the  
device thereby increasing the long term reliability.  
13  
e
e
e
g
DO  
g
g
CI , RX  
g
g
DI , TX  
g
* IEEE names for CD  
5.1 P.C. BOARD LAYOUT  
V
EE  
pins are to be connected to a copper plane which  
should be included in the printed circuit board layout. Refer  
to National Semiconductor application note AN-442 (Ether-  
net/Cheapernet Physical Layer Made Easy) for complete  
board layout instructions.  
The DP8392A package is uniquely designed to ensure that  
the device meets the 1 million hour Mean Time Between  
Failure (MTBF) requirement of the IEEE 802.3 standard. In  
order to fully utilize this heat dissipation design, the three  
5
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