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DP83910A PDF预览

DP83910A

更新时间: 2022-10-12 16:28:45
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德州仪器 - TI /
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14页 262K
描述
DP83910A CMOS SNI Serial Network Interface

DP83910A 数据手册

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9.0 Switching Characteristics (Continued)  
Transmit Timing (End of Packet)  
TL/F/9365–5  
Transmit Specifications (End of Packet)  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
t
t
t
Transmit Enable Hold Time from Rising Edge of TXC  
Transmit Output High before Idle (Half Step)  
Transmit Output Idle Time (Half Step)  
TXEh  
200  
ns  
TOh  
*
TOi  
8000  
ns  
Receive Timing (Start of Packet)  
TL/F/9365–6  
Receiver Specifications (Start of Packet)  
Symbol  
Parameter  
Min  
Max  
60  
Units  
%
t
t
t
t
t
t
t
t
t
Receive Clock Duty Cycle (Note 1)  
Receive Clock Rise Time (20% to 80%, C  
Receive Clock Fall Time (80% to 20%, C  
40  
RCd  
e
TL  
*
RCr  
30 pF)  
7
ns  
e
TL  
*
RCf  
30 pF)  
7
ns  
Carrier Sense Turn On Delay  
Decoder Acquisition Time  
Receive Data Output Delay  
70  
ns  
CRSon  
DAT  
RDd  
RDs  
Dtor  
700  
150  
ns  
ns  
Receive Data Output Stable after Going Valid  
Differential Inputs Turn-On Pulse (Note 2)  
90  
30  
ns  
ns  
Receive Data Output Valid from Falling Edge of RXC  
10  
ns  
RDV  
Note 1: This parameter is measured using the fifty percent point of each clock edge.  
b
Note 2: This parameter was characterized with a differential input of 375 mV on the receive pair inputs.  
8

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