DP83867CS, DP83867IS, DP83867E
ZHCSEC3D –OCTOBER 2015 –REVISED NOVEMBER 2022
www.ti.com.cn
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
General-Purpose I/O: This signal provides a multi-function configurable I/O.
Refer to the GPIO_MUX_CTRL register for details.
GPIO_0
39
S, O, PD
S, O, PD
General-Purpose I/O: This signal provides a multi-function configurable I/O.
Refer to the GPIO_MUX_CTRL register for details.
GPIO_1
40
MANAGEMENT INTERFACE
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial
management input and output data. This clock may be asynchronous to the
MAC transmit and receive clocks. The maximum clock rate is 25 MHz and no
minimum.
MDC
16
I, PD
I/O
MANAGEMENT DATA I/O: Bidirectional management instruction and data
signal that may be sourced by the management station or the PHY. This pin
requires pullup resistor. The IEEE specified resistor value is 1.5 kΩ, but a 2.2
kΩis acceptable.
MDIO
17
44
INTERRUPT / POWER DOWN:
The default function of this pin is POWER DOWN.
POWER DOWN: This is an Active Low Input. Asserting this signal low enables
the power-down mode of operation. In this mode, the device powers down and
consume minimum power. Register access is available through the
Management Interface to configure and power up the device.
INTERRUPT: When operating this pin as an interrupt, it is an open-drain
architecture. TI recommends using an external 2.2-kΩresistor connected to
the VDDIO supply.
INT / PWDN
I/O, PU
RESET
RESET: The active low RESET initializes or reinitializes the DP83867. All
internal registers re-initialize to their default state upon assertion of RESET.
The RESET input must be held low for a minimum of 1 µs.
RESET_N
43
I, PU
CLOCK INTERFACE
XI
15
14
18
I
CRYSTAL/OSCILLATOR INPUT: 25-MHz oscillator or crystal input (50 ppm)
CRYSTAL OUTPUT: Second terminal for 25-MHz crystal. Must be left floating if
a clock oscillator is used.
XO
O
O
CLK_OUT
CLOCK OUTPUT: Output clock
JTAG INTERFACE
JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all
test logic input and output controlled by the testing entity.
JTAG_CLK
JTAG_TDO
20
21
I, PU
O
JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most
recent test results are scanned out of the device through TDO.
JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin
sequences the Tap Controller (16-state FSM) to select the desired test
instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to
reset the JTAG.
JTAG_TMS
22
23
I, PU
I, PU
JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is
scanned into the device through TDI.
JTAG_TDI
LED INTERFACE
LED_2
LED_2: By default, this pin indicates receive or transmit activity. Additional
functionality is configurable through LEDCR1[11:8] register bits.
45
46
47
S, I/O, PD
S, I/O, PD
S, I/O, PD
LED_1: By default, this pin indicates that 1000BASE-T link is established.
Additional functionality is configurable through LEDCR1[7:4] register bits.
LED_1
LED_0
LED_0: By default, this pin indicates that link is established. Additional
functionality is configurable through LEDCR1[3:0] register bits.
MEDIA DEPENDENT INTERFACE
TD_P_A
TD_M_A
TD_P_B
TD_M_B
1
2
4
5
A
A
A
A
Differential Transmit and Receive Signals
Differential Transmit and Receive Signals
Differential Transmit and Receive Signals
Differential Transmit and Receive Signals
Copyright © 2022 Texas Instruments Incorporated
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