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DP83865DVH

更新时间： 2024-02-13 18:43:36
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口电信集成电路电信电路以太网局域网（LAN）标准
页数 文件大小 规格书
86页 589K
描述
DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer

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DP83865DVH 技术参数

生命周期：Not Recommended零件包装代码：QFP
包装说明：FQFP, QFP128,.67X.93,20针数：128
Reach Compliance Code：not_compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.98Samacsys Confidence：3
Samacsys Status：Released2D Presentation：https://componentsearchengine.com/2D/0T/154556.1.1.png
Schematic Symbol：https://componentsearchengine.com/symbol.php?partID=154556PCB Footprint：https://componentsearchengine.com/footprint.php?partID=154556
3D View：https://componentsearchengine.com/viewer/3D.php?partID=154556Samacsys PartID：154556
Samacsys Image：https://componentsearchengine.com/Images/9/DP83865DVH.jpgSamacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/DP83865DVH.jpg
Samacsys Pin Count：128Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Quad Flat PackagesSamacsys Footprint Name：VLA128A
Samacsys Released Date：2015-05-24 21:47:42Is Samacsys：N
数据速率：1000000 MbpsJESD-30 代码：R-PQFP-G128
JESD-609代码：e0长度：20 mm
湿度敏感等级：3功能数量：1
端子数量：128收发器数量：1
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP128,.67X.93,20封装形状：RECTANGULAR
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：245
电源：1.8,2.5/3.3 V认证状态：Not Qualified
座面最大高度：3.15 mm子类别：Network Interfaces
标称供电电压：1.8 V表面贴装：YES
技术：CMOS电信集成电路类型：INTERFACE CIRCUIT
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

DP83865DVH 数据手册

 浏览型号DP83865DVH的Datasheet PDF文件第3页浏览型号DP83865DVH的Datasheet PDF文件第4页浏览型号DP83865DVH的Datasheet PDF文件第5页浏览型号DP83865DVH的Datasheet PDF文件第7页浏览型号DP83865DVH的Datasheet PDF文件第8页浏览型号DP83865DVH的Datasheet PDF文件第9页 
1.0 Pin Description (Continued)  
PQFP  
Signal Name  
Type  
Description  
Pin #  
TXD0/TX0  
I
76  
TRANSMIT DATA: These signals carry 4B data nibbles (TXD[3:0]) during 10  
Mbps and 100 Mbps MII mode, 4-bit data (TX[3:0]) in RGMII mode, and 8-bit  
data (TXD[7:0]) in 1000 Mbps GMII mode. They are synchronous to the trans-  
mit clocks (TX_CLK, TCK, GTX_CLK).  
TXD1/TX1  
TXD2/TX2  
TXD3/TX3  
TXD4  
75  
72  
71  
Transmit data is input to PHY. In MII or GMII mode, the transmit data is en-  
abled by TX_EN. In RGMII mode, the transmit data is enabled by TXEN_ER.  
68  
TXD5  
67  
TXD6  
66  
TXD7  
65  
TX_EN/TXEN_ER  
I
62  
TRANSMIT ENABLE or TRANSMIT ENABLE/ERROR: In MII or GMII mode,  
it is an active high input sourced from MAC layer to indicate transmission data  
is available on the TXD.  
In RGMII mode, it combines the transmit enable and the transmit error signals  
of GMII mode using both clock edges.  
GTX_CLK/TCK  
TX_ER  
I
I
79  
61  
GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced  
from the MAC layer to the PHY. Nominal frequency is 125 MHz.  
TRANSMIT ERROR: It is an active high input used in MII mode and GMII  
mode forcing the PHY to transmit invalid symbols. The TX_ER signal is syn-  
chronous to the transmit clocks (TX_CLK or GTX_CLK).  
In MII 4B nibble mode, assertion of Transmit Error by the controller causes the  
PHY to issue invalid symbols followed by Halt (H) symbols until deassertion oc-  
curs.  
In GMII mode, assertion causes the PHY to emit one or more code-groups that  
are invalid data or delimiter in the transmitted frame.  
This signal is not used in the RGMII mode.  
RX_CLK  
O_Z  
O_Z  
57  
RECEIVE CLOCK: Provides the recovered receive clocks for different modes  
of operation:  
2.5 MHz in 10 Mbps mode.  
25 MHz in 100 Mbps mode.  
125 MHz in 1000 Mps GMII mode.  
This pin is not used in the RGMII mode.  
RXD0/RX0  
RXD1/RX1  
RXD2/RX2  
RXD3/RX3  
RXD4  
56  
55  
52  
51  
50  
47  
46  
45  
41  
RECEIVE DATA: These signals carry 4-bit data nibbles (RXD[3:0]) during 10  
Mbps and 100 Mbps MII mode and 8-bit data bytes (RXD[7:0]) in 1000 Mbps  
GMII mode. RXD is synchronous to the receive clock (RX_CLK). Receive data  
is souirced from the PHY to the MAC layer.  
Receive data RX[3:0] is used in RGMII mode. The data is synchronous to the  
RGMII receive clock (RCK). The receive data available (RXDV_EN) indicates  
valid received data to the MAC layer.  
RXD5  
RXD6  
RXD7  
RX_ER/RXDV_ER  
O_Z  
O_Z  
RECEIVE ERROR or RECEIVE DATA AVAILABLE/ERROR: In 10 Mbps,  
100 Mbps and 1000 Mbps mode this active high output indicates that the PHY  
has detected a Receive Error. The RX_ER signal is synchronous with the re-  
ceive clock (RX_CLK).  
In RGMII mode, the receive data available and receive error is combined  
(RXDV_ER) using both rising and falling edges of the receive clock (RCK).  
RX_DV/RCK  
44  
RECEIVE DATA VALID or RECEIVE CLOCK: In MII and GMII modes, it is as-  
serted high to indicate that valid data is present on the corresponding RXD[3:0]  
in MII mode and RXD[7:0] in GMII mode.  
In RGMII mode, this pin is the recovered receive clock (125MHz).  
www.national.com  
6
1...3456789...86

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