5秒后页面跳转
捷配首页

Datasheet > DP83822IFRHBT
DP83822IFRHBT PDF预览

DP83822IFRHBT

更新时间： 2024-02-19 20:49:23
品牌 Logo 应用领域
德州仪器 - TI 以太网局域网（LAN）标准以太网：16GBASE-T电信电信集成电路光纤
页数 文件大小 规格书
126页 3464K
描述
支持光纤接口、具有 16kV ESD 保护的低功耗耐用型 10/100Mbps 以太网 PHY 收发器 | RHB | 32 | -40 to 85

阅读下载

中文翻译

获取价格

DP83822IFRHBT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：1.73数据速率：100000 Mbps
JESD-30 代码：S-PQCC-N32JESD-609代码：e4
长度：5 mm湿度敏感等级：2
功能数量：1端子数量：32
收发器数量：4最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度：1 mm
标称供电电压：1.8 V表面贴装：YES
电信集成电路类型：ETHERNET TRANSCEIVER温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：5 mmBase Number Matches：1

DP83822IFRHBT 数据手册

 浏览型号DP83822IFRHBT的Datasheet PDF文件第3页浏览型号DP83822IFRHBT的Datasheet PDF文件第4页浏览型号DP83822IFRHBT的Datasheet PDF文件第5页浏览型号DP83822IFRHBT的Datasheet PDF文件第7页浏览型号DP83822IFRHBT的Datasheet PDF文件第8页浏览型号DP83822IFRHBT的Datasheet PDF文件第9页 
DP83822HF, DP83822IF, DP83822H, DP83822I  
ZHCSFD6F –JULY 2016 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Functions (continued)  
PIN  
NAME  
TYPE(1)  
DESCRIPTION  
NO.  
Collision Detect: For Full-Duplex mode, this pin is always LOW. In Half-  
Duplex mode, this pin is asserted HIGH only when both transmit and  
receive media are non-idle.  
COL / GPIO2  
29  
I/O, S-PU  
Unused in RMII Mode  
SERIAL MANAGEMENT INTERFACE  
Management Data Clock: Synchronous clock to the MDIO serial  
management input/output data. This clock may be asynchronous to the  
MAC transmit and receive clocks. The maximum clock rate is 25 MHz.  
There is no minimum clock rate.  
MDC  
20  
19  
I
Management Data I/O: Bidirectional management data signal that may  
be sourced by the management station or the PHY. This pin requires a  
2.2-kΩpullup resistor.  
MDIO  
I/O  
Interrupt / Power Down: Register access is required for this pin to be  
configured either as power down or as an interrupt. The default function  
of this pin is power down. When this pin is configured for a power down  
function, an active low signal on this pin places the device in power-down  
mode.  
INT/PWDN  
8
I/O, OD  
When this pin is configured as an interrupt pin, this pin is asserted low  
when an interrupt condition occurs. The pin has an open-drain output with  
a weak internal pullup. Some applications may require an external pullup  
resistor.  
RESET: This pin is an active low reset input that initializes or re-initializes  
all the internal registers of the PHY. Asserting this pin low for at least 10  
µs will force a reset process to occur.  
RESET  
18  
I, PU  
CLOCK INTERFACE  
Crystal / Oscillator Input  
MII reference clock: Reference clock 25-MHz ±100 ppm-tolerance  
crystal or oscillator input. The device supports either an external crystal  
resonator connected across pins XI and XO, or an external CMOS-level  
oscillator connected to pin XI only.  
RMII reference clock: Reference clock 50-MHz ±100 ppm-tolerance  
CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz ±100  
ppm-tolerance crystal or oscillator in RMII Master mode.  
RGMII reference clock:Reference clock 25-MHz ±100 ppm-tolerance  
crystal or oscillator input. The device supports either an external crystal  
resonator connected across pins XI and XO, or an external CMOS-level  
oscillator connected to pin XI only.  
XI  
23  
I
Crystal Output: Reference Clock output. XO pin is used for crystal only.  
This pin should be left floating when a CMOS-level oscillator is connected  
to XI.  
XO  
22  
17  
O
GPIO AND LED INTERFACE  
Mode 1 (Default): LINK Indication, LED indicates the status of the link.  
When the link is good, LED is ON. When the link is down, LED is OFF.  
Mode 2: ACT Indication, LED indicates transmit and receive activity in  
addition to the status of the link. The LED is ON when link is good. The  
LED blinks when the transmitter or receiver is active.  
LED_0  
O, S-PU  
Mode 1 (Default): This pin is tri-state.  
Mode 2: SPEED Indication, LED indicates the speed of the link. If speed  
is 100 Mbps, LED is ON. If speed is 10 Mbps, LED is OFF. External Pull  
resistors are required when LED is connected to this pin.  
GPIO1: This pin can be used as a GPIO when using register access.  
Signal Detect: This pin acts as Signal Detect in 100BASE-FX mode and  
shall be connected with Optical Transceiver. Signal Detect high level will  
be the VDDIO voltage level.  
LED_1 / GPIO1  
24  
I/O, S-PD  
Copyright © 2022 Texas Instruments Incorporated  
6
Submit Document Feedback  
Product Folder Links: DP83822HF DP83822IF DP83822H DP83822I  
1...3456789...126

中文翻译

下载PDF

与DP83822IFRHBT相关器件

型号 品牌 描述 获取价格 数据表
DP83822IRHBR TI 具有 16kV ESD 的低功耗耐用型 10/100Mbps 以太网 PHY 收发器 |

获取价格
DP83822IRHBT TI 具有 16kV ESD 的低功耗耐用型 10/100Mbps 以太网 PHY 收发器 |

获取价格
DP83825I TI 具有 50MHz 速率且外形尺寸超小 (3mm x 3mm) 的低功耗 10/100Mbp

获取价格
DP83825IRMQR TI 具有 50MHz 速率且外形尺寸超小 (3mm x 3mm) 的低功耗 10/100Mbp

获取价格
DP83825IRMQT TI 具有 50MHz 速率且外形尺寸超小 (3mm x 3mm) 的低功耗 10/100Mbp

获取价格
DP83826E TI 具有 MII 接口和 ENHANCED 模式的低延迟 10/100Mbps 以太网 PHY

获取价格

与DP83822IFRHBT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证