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DP83816EX

更新时间： 2024-01-26 04:00:25

品牌	Logo	应用领域
德州仪器 - TI		控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
108页	843K
描述
DP83816EX 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter-II)Extended Temperature Range 0 to 85 Degrees C

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DP83816EX 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	144
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.81	地址总线宽度：	32
边界扫描：	NO	总线兼容性：	PCI
最大时钟频率：	25 MHz	数据编码/解码方法：	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：	12.5 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G144	长度：	20 mm
低功率模式：	YES	串行 I/O 数：	4
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-10 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压：	3.63 V
最小供电电压：	2.97 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	20 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN

DP83816EX 数据手册

2.0 Pin Description

PCI Bus Interface

LQFP Pin

Symbol

AD[31-0]

No(s)

Dir

Description

66, 67, 68, 70,

71, 72, 73, 74,

78, 79, 81, 82,

83, 86, 87, 88,

101, 102, 104,

105, 106, 108,

109, 110, 112,

113, 115, 116,

118, 119, 120,

121

I/O

Address and Data: Multiplexed address and data bus. As a bus master, the

DP83816-EX will drive address during the first bus phase. During subsequent

phases, the DP83816-EX will either read or write data expecting the target to

increment its address pointer. As a bus target, the DP83816-EX will decode each

address on the bus and respond if it is the target being addressed.

CBEN[3-0]

75,

89,

100,

111

I/O

Bus Command/Byte Enable: During the address phase these signals define the

“bus command” or the type of bus transaction that will take place. During the data

phase these pins indicate which byte lanes contain valid data. CBEN[0] applies to

byte 0 (bits 7-0) and CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian

Mode. In Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and CBEN[0]

applies to byte 3 (bits 7-0).

PCICLK

Clock: This PCI Bus clock provides timing for all bus phases. The rising edge

defines the start of each phase. The clock frequency ranges from 0 to 33 MHz.

DEVSELN

I/O

Device Select: As a bus master, the DP83816-EX samples this signal to insure that

the destination address for the data transfer is recognized by a PCI target. As a

target, the DP83816-EX asserts this signal low when it recognizes its address after

FRAMEN is asserted.

FRAMEN

GNTN

I/O

Frame: As a bus master, this signal is asserted low to indicate the beginning and

duration of a bus transaction. Data transfer takes place when this signal is asserted.

It is de-asserted before the transaction is in its final phase. As a target, the device

monitors this signal before decoding the address to check if the current transaction

is addressed to it.

Grant: This signal is asserted low to indicate to the DP83816-EX that it has been

granted ownership of the bus by the central arbiter. This input is used when the

DP83816-EX is acting as a bus master.

IDSEL

INTAN

Initialization Device Select: This pin is sampled by the DP83816-EX to identify

when configuration read and write accesses are intended for it.

Interrupt A: This signal is asserted low when an interrupt condition occurs as

defined in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable

registers.

IRDYN

I/O

Initiator Ready: As a bus master, this signal will be asserted low when the

DP83816-EX is ready to complete the current data phase transaction. This signal is

used in conjunction with the TRYDN signal. Data transaction takes place at the

rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a target,

this signal indicates that the master has put the data on the bus.

PAR

I/O

Parity: This signal indicates even parity across AD[31-0] and CBEN[3-0] including

the PAR pin. As a master, PAR is asserted during address and write data phases.

As a target, PAR is asserted during read data phases.

PERRN

Parity Error: The DP83816-EX as a master or target will assert this signal low to

indicate a parity error on any incoming data (except for special cycles). As a bus

master, it will monitor this signal on all write operations (except for special cycles).

REQN

RSTN

Request: The DP83816-EX will assert this signal low to request ownership of the

bus from the central arbiter.

Reset: When this signal is asserted all PCI bus outputs of DP83816-EX will be in

TRI-STATE and the device will be put into a known state.

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