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DP83620SQE

更新时间： 2024-02-13 03:04:35
品牌 Logo 应用领域
德州仪器 - TI 以太网局域网（LAN）标准
页数 文件大小 规格书
105页 1160K
描述
DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

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DP83620SQE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN, LCC48,.27SQ,20
Reach Compliance Code：compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：8 weeks
风险等级：1.27Is Samacsys：N
数据速率：100000 MbpsJESD-30 代码：S-PQCC-N48
JESD-609代码：e3长度：7 mm
湿度敏感等级：2功能数量：1
端子数量：48收发器数量：1
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Network Interfaces
标称供电电压：3.3 V表面贴装：YES
技术：CMOS电信集成电路类型：ETHERNET TRANSCEIVER
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

DP83620SQE 数据手册

 浏览型号DP83620SQE的Datasheet PDF文件第7页浏览型号DP83620SQE的Datasheet PDF文件第8页浏览型号DP83620SQE的Datasheet PDF文件第9页浏览型号DP83620SQE的Datasheet PDF文件第11页浏览型号DP83620SQE的Datasheet PDF文件第12页浏览型号DP83620SQE的Datasheet PDF文件第13页 
DP83620  
SNLS339C –JANUARY 2011–REVISED APRIL 2013  
www.ti.com  
3.7 JTAG INTERFACE  
Signal Name  
Pin Name  
Type  
Pin #  
Description  
TCK  
TCK  
I, PU  
8
TEST CLOCK  
This pin has a weak internal pullup.  
TEST OUTPUT  
TDO  
TMS  
TDO  
TMS  
O
9
I, PU  
10  
TEST MODE SELECT  
This pin has a weak internal pullup.  
TEST RESET: Active low test reset.  
This pin has a weak internal pullup.  
TEST DATA INPUT  
TRST#  
TDI  
TRST#  
TDI  
I, PU  
I, PU  
11  
12  
This pin has a weak internal pullup.  
3.8 RESET AND POWER DOWN  
Signal Name  
Pin Name  
Type  
Pin #  
Description  
RESET_N  
RESET_N  
I, PU  
29  
RESET: Active Low input that initializes or re-initializes the DP83620.  
Asserting this pin low for at least 1 µs will force a reset process to occur.  
All internal registers will re-initialize to their default states as specified for  
each bit in the Register Block section. All strap options are re-initialized as  
well.  
PWRDOWN/INTN PWRDOWN/INTN  
I, PU  
7
The  
default  
function  
of  
this  
pin  
is  
POWER  
DOWN.  
POWER DOWN: Asserting this signal low enables the DP83620 Power  
Down mode of operation. In this mode, the DP83620 will power down and  
consume minimum power. Register access will be available through the  
Management Interface to configure and power up the device.  
INTERRUPT: This pin may be programmed as an interrupt output instead  
of a Powerdown input. In this mode, Interrupts will be asserted low using  
this pin. Register access is required for the pin to be used as an interrupt  
mechanism. See Interrupt Mechanisms for more details on the interrupt  
mechanisms.  
3.9 STRAP OPTIONS  
The DP83620 uses many of the functional pins as strap options to place the device into specific modes of  
operation. The values of these pins are sampled at power up or hard reset. During software resets, the  
strap options are internally reloaded from the values sampled at power up or hard reset. The strap option  
pin assignments are defined below. The functional pin name is indicated in parentheses.  
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default  
option is required, then there is no need for external pull-up or pull down resistors. Since these pins may  
have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.  
Signal Name  
Pin Name  
Type  
Pin #  
Description  
PHYAD0  
COL  
S, O, PU  
S, O, PD  
S, O, PD  
S, O, PD  
S, O, PD  
42  
43  
44  
45  
46  
PHY ADDRESS [4:0]: The DP83620 provides five PHY address pins,  
the state of which are latched into the PHYCTRL register at system  
Hardware-Reset.  
The DP83620 supports PHY Address strapping values 0 (<00000>)  
through 31 (<11111>).A PHY Address of 0 puts the part into the MII  
Isolate Mode. The MII isolate mode must be selected by strapping  
PHY Address 0; changing to Address 0 by register write will not put the  
PHY in the MII isolate mode.  
PHYAD1  
PHYAD2  
PHYAD3  
PHYAD4  
RXD_3  
RXD_2  
RXD_1  
RXD_0  
PHYAD[0] pin has weak internal pull-up resistor.  
PHYAD[4:1] pins have weak internal pull-down resistors.  
10  
Pin Descriptions  
Copyright © 2011–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: DP83620  
1...78910111213...105

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