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DM74LS75CW PDF预览

DM74LS75CW

更新时间: 2024-01-28 09:23:58
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
5页 53K
描述
D Latch, LS Series, 2-Func, High Level Triggered, 2-Bit, Complementary Output, TTL, WAFER

DM74LS75CW 技术参数

生命周期:Obsolete零件包装代码:WAFER
包装说明:DIE,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.7
Is Samacsys:N系列:LS
JESD-30 代码:X-XUUC-N16逻辑集成电路类型:D LATCH
位数:2功能数量:2
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
传播延迟(tpd):30 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:UPPER
触发器类型:HIGH LEVELBase Number Matches:1

DM74LS75CW 数据手册

 浏览型号DM74LS75CW的Datasheet PDF文件第2页浏览型号DM74LS75CW的Datasheet PDF文件第3页浏览型号DM74LS75CW的Datasheet PDF文件第4页浏览型号DM74LS75CW的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74LS75  
Quad Latch  
General Description  
These latches are ideally suited for use as temporary stor-  
age for binary information between processing units and  
input/output or indicator units. Information present at a data  
(D) input is transferred to the Q output when the enable is  
HIGH, and the Q output will follow the data input as long as  
the enable remains HIGH. When the enable goes LOW, the  
information (that was present at the data input at the time  
the transition occurred) is retained at the Q output until the  
enable is permitted to go HIGH.  
These latches feature complementary Q and Q outputs  
from a 4-bit latch, and are available in 16-pin packages.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS75M  
DM74LS75N  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Diagram  
Connection Diagram  
(Each Latch)  
Function Table (Each Latch)  
Inputs  
Enable  
Outputs  
D
L
Q
L
Q
H
H
H
L
H
X
H
L
Q0  
Q0  
H = HIGH Level  
L = LOW Level  
X = Don't Care  
Q
= The Level of Q Before the HIGH-to-LOW Transition of ENABLE  
0
© 2000 Fairchild Semiconductor Corporation  
DS006374  
www.fairchildsemi.com  

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