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DM74ALS373WM_NL

更新时间： 2024-01-05 02:31:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 70K
描述
Bus Driver, ALS Series, 1-Func, 8-Bit, True Output, TTL, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20

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DM74ALS373WM_NL 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：20
Reach Compliance Code：unknown风险等级：5.7
系列：ALSJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：12.8 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：16 ns
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

DM74ALS373WM_NL 数据手册

 浏览型号DM74ALS373WM_NL的Datasheet PDF文件第2页浏览型号DM74ALS373WM_NL的Datasheet PDF文件第3页浏览型号DM74ALS373WM_NL的Datasheet PDF文件第4页浏览型号DM74ALS373WM_NL的Datasheet PDF文件第5页浏览型号DM74ALS373WM_NL的Datasheet PDF文件第6页浏览型号DM74ALS373WM_NL的Datasheet PDF文件第7页 
April 1984  
Revised February 2000  
DM74ALS373  
Octal D-Type 3-STATE Transparent Latch  
General Description  
Features  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
■ Switching specifications at 50 pF  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
■ Functionally and pin for pin compatible with LS TTL  
counterpart  
■ Improved AC performance over DM74LS373 at approxi-  
mately half the power  
The eight latches of the DM74ALS373 are transparent D-  
type latches. While the enable (G) is HIGH the Q outputs  
will follow the data (D) inputs. When the enable is taken  
LOW the output will be latched at the level of the data that  
was set up.  
■ 3-STATE buffer-type outputs drive bus lines directly  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the latches. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS373WM  
DM74ALS373SJ  
DM74ALS373N  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006220  
www.fairchildsemi.com  
1234567

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