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DM74ALS374WM PDF预览

DM74ALS374WM

更新时间: 2024-11-24 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 76K
描述
Octal 3-STATE D-Type Edge-Triggered Flip-Flop

DM74ALS374WM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.09
Is Samacsys:N系列:ALS
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:35000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):31 mA传播延迟(tpd):16 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

DM74ALS374WM 数据手册

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September 1986  
Revised February 2000  
DM74ALS374  
Octal 3-STATE D-Type Edge-Triggered Flip-Flop  
General Description  
Features  
This 8-bit register features totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provides this register with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. It is particularly attractive for  
implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
Switching specifications at 50 pF  
Switching specifications guaranteed over full  
temperature and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin-for-pin compatible with LS TTL  
counterpart  
Improved AC performance over DM74LS374 at approxi-  
mately half the power  
The eight flip-flops of the DM74ALS374 are edge-triggered  
D-type flip-flops. On the positive transition of the clock, the  
Q outputs will be set to the logic states that were set up at  
the D inputs.  
3-STATE buffer-type outputs drive bus lines directly  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS374WM  
DM74ALS374SJ  
DM74ALS374N  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006113  
www.fairchildsemi.com  

DM74ALS374WM 替代型号

型号 品牌 替代类型 描述 数据表
DM74LS374WM FAIRCHILD

完全替代

3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
SN74LS374DW TI

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OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN74ALS374ADW TI

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OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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