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DM74ALS138

更新时间： 2024-09-20 22:56:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解复用器
页数 文件大小 规格书
6页 69K
描述
3 to 8 Line Decoder/Demultiplexer

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中文翻译

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DM74ALS138 数据手册

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September 1986  
Revised February 2000  
DM74ALS138  
3 to 8 Line Decoder/Demultiplexer  
General Description  
Features  
These Schottky-clamped circuits are designed to be used  
in high-performance memory-decoding or data-routing  
applications, requiring very short propagation delay times.  
In high-performance memory systems these decoders can  
be used to minimize the effects of system decoding. When  
used with high-speed memories, the delay times of these  
decoders are usually less than the typical access time of  
the memory. This means that the effective system delay  
introduced by the decoder is negligible.  
■ Designed specifically for high speed:  
Memory decoders  
Data transmission systems  
■ 3- to 8-line decoder incorporates 3 enable inputs to sim-  
plify cascading and/or data reception  
■ Low power dissipation…23 mW typ  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
The DM74ALS138 decodes one-of-eight lines, based upon  
the conditions at the three binary select inputs and the  
three enable inputs. Two active-LOW and one active-HIGH  
enable inputs reduce the need for external gates or invert-  
ers when expanding. A 24-line decoder can be imple-  
mented with no external inverters, and 32-line decoder  
requires only one inverter. An enable input can be used as  
a data input for demultiplexing applications.  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
This decoder/demultiplexer features fully buffered inputs,  
presenting only one normalized load to its driving circuit. All  
inputs are clamped with high-performance Schottky diodes  
to suppress line-ringing and simplify system design.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS138M  
DM74ALS138SJ  
DM74ALS138N  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Enable  
Inputs  
Select  
Inputs  
Outputs  
G1  
G2  
C
B
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
(Note 1)  
X
L
H
X
L
L
L
L
L
L
L
L
X
X
L
X
X
L
X
X
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Note 1: G2 = G2A + G2B  
© 2000 Fairchild Semiconductor Corporation  
DS006111  
www.fairchildsemi.com  
123456

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