DLP3010LC
DLPS179C – APRIL 2020 – REVISED JULY 2023
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN
–0.5
–0.5
–0.5
MAX
2.3
2.3
11
UNIT
Supply voltage for LVCMOS core logic(2)
Supply voltage for LPSDR low speed interface
VDD
V
V
V
VDDI
Supply voltage for SubLVDS receivers(2)
Supply voltage for HVCMOS and micromirror
electrode(2) (3)
VOFFSET
Supply voltage for micromirror electrode(2)
Supply voltage for micromirror electrode(2)
Supply voltage delta (absolute value)(4)
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
–0.5
–15
19
0.5
V
V
Supply voltage
VBIAS
VRESET
| VDDI–VDD |
| VBIAS–VOFFSET |
| VBIAS–VRESET |
0.3
V
11
V
34
V
Input voltage for other inputs LPSDR(2)
–0.5
–0.5
VDD + 0.5
VDDI + 0.5
810
V
Input voltage
Input pins
Input voltage for other inputs SubLVDS(2) (7)
V
| VID |
IID
SubLVDS input differential voltage (absolute value)(7)
mV
mA
MHz
MHz
°C
°C
SubLVDS input differential current
10
ƒclock
ƒclock
Clock frequency for low speed interface LS_CLK
Clock frequency for high speed interface DCLK
Temperature – operational (8)
130
Clock
frequency
560
–20
–40
90
TARRAY and TWINDOW
Temperature – non-operational(8)
90
Dew Point Temperature - operating and non-operating
(non-condensing)
Environmental
TDP
|TDELTA
81
30
°C
°C
Absolute Temperature delta between any point on the
window edge and the ceramic test point TP1(9)
|
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current
draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated by the Section 7.6) or of any point along the Window Edge as defined
in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge
temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be
used.
(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
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6
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