DLP3010
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ZHCSHW7B –FEBRUARY 2018 –REVISED MAY 2022
5 Pin Configuration and Functions
图5-1. FQK Package. 57-Pin LGA. BOTTOM VIEW.
表5-1. Pin Functions –Connector Pins
PIN(1)
NAME
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
DATA INPUTS
D_N(0)
C9
B9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Data, Negative
10.54
10.54
13.14
13.14
14.24
14.24
14.35
14.35
5.89
D_P(0)
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Clock, Negative
Clock, Positive
D_N(1)
D10
D11
C11
B11
D12
D13
D4
D_P(1)
D_N(2)
D_P(2)
D_N(3)
D_P(3)
D_N(4)
D_P(4)
D5
5.89
D_N(5)
C5
5.45
D_P(5)
B5
5.45
D_N(6)
D6
8.59
D_P(6)
D7
8.59
D_N(7)
C7
7.69
D_P(7)
B7
7.69
DCLK_N
DCLK_P
CONTROL INPUTS
LS_WDATA
LS_CLK
D8
8.10
D9
8.10
C12
C13
I
I
LPSDR(1)
LPSDR
Single
Single
Write data for low-speed interface.
Clock for low-speed interface.
7.16
7.89
Asynchronous reset DMD signal. A low
signal places the DMD in reset. A high
signal releases the DMD from reset
and places it in active mode.
DMD_DEN_ARSTZ C14
I
LPSDR
LPSDR
LS_RDATA
POWER
VBIAS(3)
VBIAS(3)
C15
O
Single
Read data for low-speed interface.
C1
Power
Power
Supply voltage for positive bias level at
micromirrors.
C18
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