CONTROL REGISTER
STATUS REGISTER
A 16-bit control register is used to configure the device.
The control register bits CR0 – CR15 are loaded from
BD00 – BD15 when /CWSTR is pulsed low. The control
register contents are output on the data bus when SEL = 1
and /RSR is pulsed low. Each bit of the control register
has the following function:
The device contains a 9-bit status register which can be
interrogated to determine the status of the ARINC
receivers, data FIFOs and transmitter. The contents of the
status register are output on BD0 - BD08 when the /RSR
pin is taken low and SEL = 0. Unused bits are output as
zeros. The following table defines the status register bits.
Table 2: Control Register Bit definition
Table 3: Status Register Bit Definition
CR Bit FUNCTION STATE
DESCRIPTION
Data rate HI = CLK/10
Data rate LO= CLK/80
SR Bit
FUNCTION STATE
DESCRIPTION
Receiver 1 FIFO empty
CR0
CR1
CR2
CR3
Receiver 1
Data clock
Select
0
1
SR0
Data ready
0
1
(Receiver 1)
Receiver 1 FIFO contains valid
data. Resets to zero when all data
has been read. /DR1 pin is the
inverse of this bit
Label
0
1
Normal operation
Memory
Load 16 labels using /PL1,/PL2
Read 16 labels using /EN1, /EN2
Disable label recognition
Read/Write
Enable Label
Recognition
(Receiver 1)
Enable Label
Recognition
(Receiver 2)
Enable 32nd
bit as parity
SR1
SR2
SR3
SR4
SR5
FIFO
half full
0
1
Receiver 1 FIFO holds less than
16 words
0
(Receiver 1)
Receiver 1 FIFO holds at least 16
words. /HF1 pin is the inverse of
this bit
1
0
1
Enable label recognition
Disable label recognition
Enable label recognition
FIFO full
0
1
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid
data loss, the FIFO must be read
within one ARINC word period.
/FF1 pin is the inverse of this bit.
Receiver 2 FIFO empty
(Receiver 1)
CR4
CR5
0
1
0
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
The 429DO and /429DO digital
outputs are internally connected to
the Rx logic inputs
Self Test
Data ready
0
1
(Receiver 2)
Receiver 2 FIFO contains valid
data. Resets to zero when all data
has been read. /DR2 pin is the
inverse of this bit
1
0
1
Normal operation
CR6
Receiver 1
decoder
Receiver 1 decoder disabled
ARINC bits 9 and 10 must match
CR7 and CR8
FIFO
half full
0
1
Receiver 2 FIFO holds less than
16 words
CR7
CR8
CR9
-
-
-
-
If receiver 1 decoder is enabled, the
ARINC bit 9 must match this bit
If receiver 1 decoder is enabled, the
ARINC bit 10 must match this bit
Receiver 2 decoder disabled
ARINC bits 9 and 10 must match
CR10 and CR11
(Receiver 2)
Receiver 2 FIFO holds at least 16
words. /HF2 pin is the inverse of
this bit
FIFO full
0
1
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid
data loss, the FIFO must be read
within one ARINC word period.
/FF2 pin is the inverse of this bit.
Transmitter FIFO not empty
Transmitter FIFO empty
Transmitter FIFO not full
Transmitter FIFO full. /FFT pin
is the inverse of this bit
Receiver 2
decoder
0
1
(Receiver 2)
CR10
CR11
CR12
-
-
-
-
If receiver 2 decoder is enabled, the
ARINC bit 9 must match this bit
SR6
SR7
Transmitter
FIFO empty
Transmitter
FIFO full
0
1
0
1
If receiver 2 decoder is enabled, the
ARINC bit 10 must match this bit
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
Invert
Transmitter
parity
0
1
SR8
Transmitter
FIFO
0
1
Transmitter FIFO contains less
than 16 words
CR13
CR14
CR15
Transmitter
data clock
select
0
1
Data rate = HI = CLK/10
Data rate = LO = CLK/80
half full
Transmitter FIFO contains at least
16 words. /HFT pin is the inverse
of this bit
Receiver 2
Data clock
Select
0
1
Data rate = HI = CLK/10
Data rate = LO = CLK/80
Data format
0
1
Scramble ARINC data
Unscramble ARINC data
©2015 Device Engineering Inc.
4 of 15
DS-MW-01084-02 Rev. H
11/24/2015
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