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DEI1282-SES PDF预览

DEI1282-SES

更新时间: 2024-02-04 01:45:45
品牌 Logo 应用领域
DEIAZ IOT光电二极管接口集成电路
页数 文件大小 规格书
17页 992K
描述
8CH BIT PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INTERFACE IC

DEI1282-SES 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:PLASTIC, MS-012AC, SOIC-16针数:16
Reach Compliance Code:not_compliant风险等级:5.14
接口集成电路类型:INTERFACE CIRCUITJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:HSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.91 mmBase Number Matches:1

DEI1282-SES 数据手册

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FUNCTIONAL DESCRIPTION  
DEI1282 and DEI1284 are eight-channel discrete-to-digital interface ICs implemented in a High Voltage Dielectric Isolated  
technology. They sense eight discrete signals of the type commonly found in avionic systems and convert them to serial logic  
data. Each input can be individually configured as either GND/OPEN or 28V/OPEN format input via a serial data input. The  
discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible  
with the industry standard Serial Peripheral Interface (SPI) bus.  
The discrete inputs are implemented with a high voltage technology to provide immunity to lightning induced transients. The  
DEI1282 tolerates DO160F Level 3 (600V) stress directly to the input pins without the need for additional protection  
components.  
The DEI1284 version operates with 3K Ohm off-chip series resistors on the inputs. These are used in combination with  
Transient Voltage Suppressor (TVS) devices to achieve Level 4 (1500V) and Level 5 (3200V) immunity. The resistors act to  
limit surge current, thus allowing small TVS devices. The resistors are also used to implement low pass filtering by adding  
capacitors on the inputs. The filtering provides noise rejection and anti-aliasing of the sampled signal.  
The on-chip Built-in Test (BIT) feature provides a Test Mode which provides a means to inject a test signal into each input  
comparator without interfering with the discrete input signals. The test coverage includes each DIN comparator as well as the  
digital logic and IO.  
Table 1 Pin Descriptions  
PINS  
NAME  
DESCRIPTION  
1-8  
DIN[1:8]  
Discrete Inputs. Eight discrete signals which can be individually  
configured as either GND/OPEN or 28V/OPEN format inputs.  
Logic Output. Serial Data Output. This pin is the output from MSB (Bit  
8) of the selected shift register (Data/Configuration). It is clocked by the  
rising edge of SCLK. This is a 3-state output enabled by /CS.  
Logic Input. Serial Shift Clock. A low-to-high transition on this input  
shifts data on the serial data input into Bit 0 of the selected shift register.  
The selected shift register is shifted from Bit 1 to Bit 8. Bit 8 of the  
selected shift register is driven on SDO.  
9
SDO  
10  
SCLK  
11  
/CS  
Logic Input. Chip Select. A low level on this input enables the SDO 3-  
state output and the selected shift register. A high level on this input  
forces SDO to the high impedance state and disables the shift registers so  
SCLK transitions have no effect. When the Data Register is selected, a  
high-to-low transition causes the Discrete Input data to be loaded into the  
Data Register. When the Configuration Register is selected, a low-to-  
high transition causes the Serial Configuration Register data to be loaded  
into the parallel configuration outputs.  
12  
13  
SDI  
Logic Input. Serial Data Input. Data on this input is shifted into the LSB  
(Bit 1) of the selected shift register on the rising edge of the SCLK when  
/CS input is low.  
Logic Input. Selects between the Data Register and Configuration  
Register. H = DATA, L = CONF.  
SEL  
14  
15  
16  
VCC  
GND  
VDD  
Logic Supply Voltage. 3.3V+/-5%  
Logic/Signal Ground  
Analog Supply Voltage. 12V to 16.5V  
©2018 Device Engineering Inc.  
2 of 17  
DS-MW-01282-01 Rev. L  
05/18/2018  

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