FUNCTIONAL DESCRIPTION
DEI1282 and DEI1284 are eight-channel discrete-to-digital interface ICs implemented in a High Voltage Dielectric Isolated
technology. They sense eight discrete signals of the type commonly found in avionic systems and convert them to serial logic
data. Each input can be individually configured as either GND/OPEN or 28V/OPEN format input via a serial data input. The
discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible
with the industry standard Serial Peripheral Interface (SPI) bus.
The discrete inputs are implemented with a high voltage technology to provide immunity to lightning induced transients. The
DEI1282 tolerates DO160F Level 3 (600V) stress directly to the input pins without the need for additional protection
components.
The DEI1284 version operates with 3K Ohm off-chip series resistors on the inputs. These are used in combination with
Transient Voltage Suppressor (TVS) devices to achieve Level 4 (1500V) and Level 5 (3200V) immunity. The resistors act to
limit surge current, thus allowing small TVS devices. The resistors are also used to implement low pass filtering by adding
capacitors on the inputs. The filtering provides noise rejection and anti-aliasing of the sampled signal.
The on-chip Built-in Test (BIT) feature provides a Test Mode which provides a means to inject a test signal into each input
comparator without interfering with the discrete input signals. The test coverage includes each DIN comparator as well as the
digital logic and IO.
Table 1 Pin Descriptions
PINS
NAME
DESCRIPTION
1-8
DIN[1:8]
Discrete Inputs. Eight discrete signals which can be individually
configured as either GND/OPEN or 28V/OPEN format inputs.
Logic Output. Serial Data Output. This pin is the output from MSB (Bit
8) of the selected shift register (Data/Configuration). It is clocked by the
rising edge of SCLK. This is a 3-state output enabled by /CS.
Logic Input. Serial Shift Clock. A low-to-high transition on this input
shifts data on the serial data input into Bit 0 of the selected shift register.
The selected shift register is shifted from Bit 1 to Bit 8. Bit 8 of the
selected shift register is driven on SDO.
9
SDO
10
SCLK
11
/CS
Logic Input. Chip Select. A low level on this input enables the SDO 3-
state output and the selected shift register. A high level on this input
forces SDO to the high impedance state and disables the shift registers so
SCLK transitions have no effect. When the Data Register is selected, a
high-to-low transition causes the Discrete Input data to be loaded into the
Data Register. When the Configuration Register is selected, a low-to-
high transition causes the Serial Configuration Register data to be loaded
into the parallel configuration outputs.
12
13
SDI
Logic Input. Serial Data Input. Data on this input is shifted into the LSB
(Bit 1) of the selected shift register on the rising edge of the SCLK when
/CS input is low.
Logic Input. Selects between the Data Register and Configuration
Register. H = DATA, L = CONF.
SEL
14
15
16
VCC
GND
VDD
Logic Supply Voltage. 3.3V+/-5%
Logic/Signal Ground
Analog Supply Voltage. 12V to 16.5V
©2018 Device Engineering Inc.
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DS-MW-01282-01 Rev. L
05/18/2018