DAC8411IDCKT

更新时间： 2024-01-01 09:42:43

品牌	Logo	应用领域
德州仪器 - TI		转换器
页数	文件大小	规格书
38页	2077K
描述
1.8V to 5.5V, 80mA, 14- and 16-Bit, Low-Power, Single-Channel, DIGITAL-TO-ANALOG CONVERTERS in SC70 Package

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DAC8411IDCKT 数据手册

DAC8311

DAC8411

SBAS439–AUGUST 2008 ................................................................................................................................................................................................ www.ti.com

SERIAL WRITE OPERATION: 14-Bit (DAC8311)

t₉

t₁

SCLK

t₈

t₂

t₃

t₇

t₄

SYNC

t₁₀

t₆

t₅

DB15

D_IN

DB0

DB15

TIMING REQUIREMENTS⁽¹⁾⁽²⁾

All specifications at –40°C to +125°C, and AV_DD= +1.8V to +5.5V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

MIN TYP MAX UNIT

(3)

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK rising edge setup time

Data setup time

4.5

Data hold time

4.5

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

100

16th SCLK falling edge to SYNC falling edge

100

SYNC rising edge to 16th SCLK falling edge

(for successful SYNC interrupt)

t₁₀

(1) All input signals are specified with t_R= t_F= 3ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

(2) See 14-Bit Serial Write Operation timing diagram.

(3) Maximum SCLK frequency is 50MHz at AV_DD= 3.6V to 5.5V and 20MHz at AV_DD= 1.8V to 3.6V.

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Product Folder Link(s): DAC8311 DAC8411

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