NRND: Not recommended for new designs.
Stellaris® LM3S608 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 19
About This Document .................................................................................................................... 23
Audience .............................................................................................................................................. 23
About This Manual ................................................................................................................................ 23
Related Documents ............................................................................................................................... 23
Documentation Conventions .................................................................................................................. 24
1
Architectural Overview .......................................................................................... 26
Product Features .......................................................................................................... 26
Target Applications ........................................................................................................ 32
High-Level Block Diagram ............................................................................................. 32
Functional Overview ...................................................................................................... 34
1.1
1.2
1.3
1.4
1.4.1 ARM Cortex™-M3 ......................................................................................................... 34
1.4.2 Motor Control Peripherals .............................................................................................. 35
1.4.3 Analog Peripherals ........................................................................................................ 35
1.4.4 Serial Communications Peripherals ................................................................................ 36
1.4.5 System Peripherals ....................................................................................................... 37
1.4.6 Memory Peripherals ...................................................................................................... 38
1.4.7 Additional Features ....................................................................................................... 38
1.4.8 Hardware Details .......................................................................................................... 39
2
2.1
2.2
The Cortex-M3 Processor ...................................................................................... 40
Block Diagram .............................................................................................................. 41
Overview ...................................................................................................................... 42
2.2.1 System-Level Interface .................................................................................................. 42
2.2.2 Integrated Configurable Debug ...................................................................................... 42
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 43
2.2.4 Cortex-M3 System Component Details ........................................................................... 43
2.3
Programming Model ...................................................................................................... 44
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 44
2.3.2 Stacks .......................................................................................................................... 44
2.3.3 Register Map ................................................................................................................ 45
2.3.4 Register Descriptions .................................................................................................... 46
2.3.5 Exceptions and Interrupts .............................................................................................. 59
2.3.6 Data Types ................................................................................................................... 59
2.4
Memory Model .............................................................................................................. 59
2.4.1 Memory Regions, Types and Attributes ........................................................................... 60
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 61
2.4.3 Behavior of Memory Accesses ....................................................................................... 61
2.4.4 Software Ordering of Memory Accesses ......................................................................... 62
2.4.5 Bit-Banding ................................................................................................................... 63
2.4.6 Data Storage ................................................................................................................ 65
2.4.7 Synchronization Primitives ............................................................................................. 66
2.5
Exception Model ........................................................................................................... 67
2.5.1 Exception States ........................................................................................................... 68
2.5.2 Exception Types ............................................................................................................ 68
2.5.3 Exception Handlers ....................................................................................................... 70
June 18, 2012
3
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