DAC81402, DAC61402
ZHCSLN9A –OCTOBER 2020 –REVISED MAY 2021
www.ti.com.cn
表6-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
Serial interface data input. Data are clocked into the input shift register on each falling edge of the
SCLK pin.
11
SDIN
Input
Input
Input
Active low serial data enable. This input is the frame synchronization signal for the serial data.
The serial serial interface input shift register is enabled when SYNC is low.
12
13
SYNC
LDAC
Active low synchronization signal. The DAC outputs of those channels configured in synchronous
mode are updated simultaneously when the LDAC pin is low. Connect to IOVDD if unused.
14
15
GND
Ground
Power
Digital ground reference point.
IOVDD
IO supply voltage. This pin sets the digital I/O operating voltage for the device.
Active-low clear input. Logic low on this pin clears all outputs to their clear code. Connect to
IOVDD if unused.
16
17
CLR
Input
OUTB
Output
Channel-B analog output voltage.
Channel-B external compensation capacitor connection pin.
The addition of an external capacitor improves the output buffer stability with high capacitive
loads at the OUTB pin by reducing the bandwidth of the output amplifier at the expense of
increased settling time.
18
CCOMPB
Input
19
20
21
22
23
24
25
SENSEPB
SENSENB
NC
Input
Input
Channel-B sense pin for the positive voltage output load connection.
Channel-B sense pin for the negative voltage output load connection.
No connection.
—
—
NC
No connection.
NC
No connection.
—
NC
No connection.
—
REFGND
Ground
Ground reference point for the internal reference.
Reference input to the device when operating with an external reference. Reference output
voltage pin when using the internal reference. Connect a 150-nF capacitor to ground.
26
REFIO
Input/Output
27
28
29
30
AVSS
AVDD
AGND
DVDD
Power
Power
Ground
Power
Output buffers negative supply voltage.
Output buffers positive supply voltage.
Analog ground reference point.
Digital and analog supply voltage.
FAULT is an open-drain, fault-condition output. An external 10-kΩpullup resistor to a voltage no
higher than IOVDD is required.
31
32
FAULT
RST
Output
Input
—
Active-low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
Thermal
Pad
The thermal pad is located on the package underside. The thermal pad should be connected to
any internal PCB ground plane through multiple vias for good thermal performance.
Thermal pad
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