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DAC53001RTER PDF预览

DAC53001RTER

更新时间: 2023-09-03 20:31:58
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
87页 3557K
描述
具有 I²C、SPI 和 PWM 的超低功耗单通道 10 位智能 DAC | RTE | 16 | -40 to 125

DAC53001RTER 数据手册

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DAC53001, DAC53002, DAC63001, DAC63002  
www.ti.com.cn  
ZHCSQK5 MAY 2022  
5 Pin Configuration and Functions  
FB0  
OUT0  
NC  
1
2
3
4
12  
11  
10  
9
FB1/NC  
OUT1/NC  
NC  
Thermal Pad  
NC  
NC  
Not to scale  
5-1. RTE Package, 16-pin WQFN, Top View  
5-1. Pin Functions  
PIN  
TYPE  
DESCRIPTION  
NO.  
NAME  
Voltage feedback pin for channel 0.  
1
FB0  
Input  
In voltage-output mode, connect to OUT0 for closed-loop amplifier output.  
In current-output mode, keep the FB0 pin unconnected to minimize leakage current.  
2
3
4
OUT0  
NC  
Output  
NC  
Analog output voltage from DAC channel 0.  
No connection. Leave this pin unconnected.  
NC  
NC  
No connection. Leave this pin unconnected.  
General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS.  
5
6
7
8
GPIO/SDO  
SCL/SYNC  
A0/SDI  
Input/Output For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor.  
If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.  
I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external  
pullup resistor. This pin can ramp up before VDD.  
Output  
Address configuration pin for I2C or serial data input for SPI.  
Input  
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (7.5.2.2.1).  
For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD.  
Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external  
pullup resistor in the I2C mode. This pin can ramp up before VDD.  
SDA/SCLK  
Input/Output  
9
NC  
NC  
NC  
NC  
No connection. Leave this pin unconnected.  
No connection. Leave this pin unconnected.  
10  
DAC63002 and DAC53002: Analog output voltage from DAC channel 1.  
DAC63001 and DAC53001: No connection. Leave this pin unconnected.  
11  
12  
OUT1/NC  
FB1/NC  
Output/NC  
Input/NC  
DAC63002 and DAC53002: Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-  
loop amplifier output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current.  
DAC63001 and DAC53001: No-connect. Leave this pin unconnected.  
13  
14  
15  
CAP  
AGND  
VDD  
Power  
Ground  
Power  
External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.  
Ground reference point for all circuitry on the device.  
Supply voltage.  
External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.  
Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case  
an external reference is used, make sure the reference ramps up after VDD.  
16  
VREF  
Power  
Copyright © 2022 Texas Instruments Incorporated  
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3
Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002  
 
 

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