Datasheet > DAC488HR/4

DAC488HR/4

更新时间： 2022-11-26 06:08:56

品牌	Logo	应用领域
其他 - ETC		转换器
页数	文件大小	规格书
4页	193K
描述
16-bit D/A Converter with Digital I/O & IEEE 488

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中文翻译

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数据手册

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DAC488HR/4 数据手册

™

DAC488HR

General Information

the smart approach to instrumentation^™

Functional Requirement

Waveform(s)

Typical Application

Continuously output a standard

wave function under program

control

Standard function generator

outputs for general purpose

applications

Sequenced V out for controlling

power supplies or other analog

programmable instruments

Output a series of voltage values

based on TTL triggers

Analog output signal

trigger event

Allows a device under test (DUT)

to attain a steady state prior to

measurement

Initiate a trigger delay from 1 to

65,535 update clock pulses

trigger delay

Synchronously output multiple

waveforms under program

control

Ideal for stimulus/response

applications with critical time

and phase relationships

Output a standard waveform

acquired by the ADC488A series

digitizer

Ideal for simulating complex

signals such as EKGs and

contact bounce

For audio system testing, speech

research, and other tests

requiring long-time waveform

generation

Continuously output a large

arbitrary waveform from the IEEE

488 bus at up to 200 Kbytes/s

Stimulus/ Response System Multi-DAC488HR

Support Software

When configured with an ADC488A se-

The DAC488HR series is shipped with

QuickBasic^®and C sample programs.

Synchronization

riesA/Dconverter,theDAC488HRiswell-

suited for stimulus/response testing. For

synchronous operation in which acquisi-

tion must begin simultaneously with the

stimulus output, the DAC488HR’s TTL

trigger output is connected directly with

theADC488A’sTTLtriggerinput;fornon-

synchronous operation in which acquisi-

tion must begin at a specified time after

thestimulusoutput,theDAC488HR’strig-

ger output can be “delayed” up to 65,535

update clock counts.

Multiple DAC488HRs can be configured

in master/slave mode to synchronously

output data either from their internal

buffers, or continuously from the IEEE

488 bus. When daisy-chained together

using the CA-112 master-slave cable, the

number of DAC488HRs in a system is

limited only by the number of available

IEEE 488 addresses, and the trigger “la-

tency” between each unit is 60 ns*. For

applicationsthatrequirenon-additivetrig-

ger latencies, the DAC488HRs can be con-

figured in parallel, limiting total system

trigger latency to 60 ns.

Free VIs (Virtual Instruments) are avail-

able from IOtech that enable the immedi-

ate integration of the DAC488HR series

intoexistingLabVIEW^®applications.Each

oftheseready-to-useVIsprovideimmedi-

ate access to common DAC488HR func-

tions, and both include source code that

can be modified to meet specific

application requirements.

A system with one master and three slave units will have a total system trigger latency of 180 ns

Q U I C K F I N D

tel: 440-439-4091 fax: 440-439-4093

sales@iotech.com

www.iotech.com

250

1 234

中文翻译

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DAC53004RTER	TI	获取价格	具有 I2C、SPI 和 PWM 的超低功耗 4 通道 10 位智能 DAC \| RTE

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