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DAC1218 PDF预览

DAC1218

更新时间: 2024-01-01 03:40:59
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
12页 229K
描述
12-Bit Binary Multiplying D/A Converter

DAC1218 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP18,.3Reach Compliance Code:unknown
风险等级:5.92转换器类型:D/A CONVERTER
JESD-30 代码:R-XDIP-T18JESD-609代码:e0
最大线性误差 (EL):0.012%位数:12
功能数量:1端子数量:18
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP18,.3封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
子类别:Other Converters表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL

DAC1218 数据手册

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Application Hints (Continued)  
A1  
2
A2  
4
A3  
8
A12  
e b  
a
a
a
. . .  
V
OUT  
V
REF  
4096  
#
J
e
where: AN 1 if digital input is high  
TL/H/5691–5  
e
AN 0 if digital input is low  
FIGURE 2. Unipolar Output Voltage  
TL/H/5691–6  
FIGURE 3. Zeroing an Amplifier Which Does Not Have Balancing Provisions  
The selected amplifier should have as low an input bias  
2.3 Output Settling Time  
current as possible since input bias current contributes to  
the current flowing through the feedback resistor. BI-FETTM  
op amps such as the LF356 or LF351 or bipolar op amps  
with super b input transistors like the LM11 or LM308A pro-  
duce negligible errors.  
The output voltage settling time for this circuit in response  
to a change of the digital input code (a full-scale change is  
the worst case) is a combination of the DAC’s output current  
settling characteristics and the settling characteristics of the  
output amplifier. The amplifier settling is further degraded by  
a feedback pole formed by the feedback resistance and the  
DAC output capacitance (which varies with the digital code).  
First order compensation for this pole is achieved by adding  
2.2 Zero and Full-Scale Adjustments  
The fundamental purpose is to make the output voltages as  
near 0 V  
as possible. This is accomplished in the circuit  
DC  
of Figure 2 by shorting out the amplifier feedback resist-  
ance, and adjusting the V nulling potentiometer of the op  
a feedback zero with capacitor C shown in Figure 2.  
C
In many applications output response time and settling is  
just as important as accuracy. It can be difficult to find a  
single op amp that combines excellent DC characteristics  
OS  
amp until the output reads zero volts. This is done, of  
course, with an applied digital input of all zeros if I is  
OUT1  
). The feedback short  
(low V , V drift and bias current) with fast response and  
OS OS  
driving the op amp (all ones for I  
OUT2  
is then removed and the converter is zero adjusted.  
settling time. BI-FET op amps offer a reasonable compro-  
mise of high speed and good DC characteristics. The circuit  
of Figure 4 illustrates a composite amplifier connection that  
combines the speed of a BI-FET LF351 with the excellent  
DC input characteristics of the LM11. If output settling time  
is not so critical, the LM11 can be used alone.  
A unique characteristic of these DACs is that any full-scale  
or gain error is always negative. This means that for a full-  
scale input code the output voltage, if not inherently correct,  
will always be less than what it should be. This ensures that  
adding an appropriate resistance in series with the internal  
Figure 5 is a settling time test circuit for the complete volt-  
age output DAC circuit. The circuit allows the settling time of  
the DAC amplifier to be measured to a resolution of 1 mV  
feedback resistor, R , will always correct for any gain error.  
Fb  
The 50X potentiometer in Figure 2 is all that is needed to  
adjust the worst case DAC gain error.  
g
out of a zero to 10V full-scale output change on an oscil-  
Conversion accuracy is only as good as the applied refer-  
ence voltage, so providing a source that is stable over time  
and temperature is important.  
loscope. Figure 6 summarizes the measured settling times  
for several output amplifiers and feedback compensation  
capacitors.  
6

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