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DAC08Q/883 PDF预览

DAC08Q/883

更新时间: 2024-01-03 05:45:26
品牌 Logo 应用领域
亚德诺 - ADI 输入元件转换器
页数 文件大小 规格书
20页 378K
描述
IC PARALLEL, 8 BITS INPUT LOADING, 0.085 us SETTLING TIME, 8-BIT DAC, CDIP16, GLASS SEALED, CERDIP-16, Digital to Analog Converter

DAC08Q/883 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5转换器类型:D/A CONVERTER
输入位码:BINARY, OFFSET BINARYJESD-30 代码:R-XDIP-T16
JESD-609代码:e0最大线性误差 (EL):0.19%
标称负供电电压:-15 V位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:+-15 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
最大稳定时间:0.15 µs子类别:Other Converters
最大压摆率:7.8 mA标称供电电压:15 V
表面贴装:NO技术:BIPOLAR
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

DAC08Q/883 数据手册

 浏览型号DAC08Q/883的Datasheet PDF文件第12页浏览型号DAC08Q/883的Datasheet PDF文件第13页浏览型号DAC08Q/883的Datasheet PDF文件第14页浏览型号DAC08Q/883的Datasheet PDF文件第16页浏览型号DAC08Q/883的Datasheet PDF文件第17页浏览型号DAC08Q/883的Datasheet PDF文件第18页 
DAC08  
RC damping of the output is difficult to prevent while main-  
taining adequate sensitivity. However, the major carry from  
01111111 to 10000000 provides an accurate indicator of settling  
time. This code change does not require the normal 6.2 time  
constants to settle to within ±0.2% of the final value, and thus  
minor sacrifice in settling time. Fastest operation can be  
obtained by using short leads, minimizing output capacitance  
and load resistor values, and by adequate bypassing at the  
supply, reference, and VLC terminals. Supplies do not require  
large electrolytic bypass capacitors because the supply current  
drain is independent of input logic states; 0.1 µF capacitors at  
the supply pins provide full transient protection.  
settling time is observed at lower values of IREF  
.
DAC08 switching transients or “glitches” are very low and can  
be further reduced by small capacitive loads at the output at a  
V
+5V  
L
FORTURN-ON, V =2.7V  
L
FORTURN-OFF, V =0.7V  
L
1µF  
1kΩ  
50µF  
1µF  
MINIMUM  
CAPACITANCE  
Q2  
1kΩ  
V
1×  
OUT  
PROBE  
V
CL  
0.7V  
+0.4V  
0V  
0V  
Q1  
V
8
0.1µF  
IN  
–0.4V  
0.1µF  
15kΩ  
R
REF  
100kΩ  
2kΩ  
5
6
9 10 11 12  
7
+V  
REF  
14  
15  
4
I
OUT  
DAC08  
R15  
2
13  
3
16  
–15V  
0.01µF  
0.1µF  
0.1µF  
+15V –15V  
Figure 33. Settling Time Measurement  
Rev. C | Page 15 of 20  

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