DAC08
(@ VS = ؎15 V, IREF = 2.0 mA; TA = 25؇C, unless otherwise noted. Output characteristics apply to both
I
IOUT and OUT .)
WAFER TEST LIMITS
DAC08N
Limit
DAC08G
Limit
DAC08GR
Limit
Parameter
Symbol
Conditions
Unit
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full-Scale Current
8
8
8
8
8
8
Bits min
Bits min
% FS max
V max
NL
VOC
0.1
+18
–10
2.04
1.94
8
0.19
+18
–10
2.04
1.94
8
0.39
+18
–10
2.04
1.94
16
Full-Scale Current
Change < 1/2 LSB
VREF = 10.000 V
V min
I
FS4 or
mA max
mA min
µA max
µA max
IFS2
IFSS
IZS
R14, R15 = 5.000 kΩ
Full-Scale Symmetry
Zero-Scale Current
Output Current Range
2
4
4
I
FS1 or
V– = –10 V,
V
REF = +15 V
2.1
4.2
2.1
4.2
2.1
4.2
mA min
mA min
V– = –12 V,
VREF = +25 V
IFS2
R
14, R15 = 5.000 kΩ
Logic Input “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic “1”
Logic Input Swing
VIL
VIH
0.8
2
0.8
2
0.8
2
V max
V min
V
LC = 0 V
IIL
IIH
VIS
VIN = –10 V to +0.8 V
VIN = +2.0 V to +18 V
V– = –15 V
10
10
+18
–10
–3
10
10
+18
–10
–3
10
10
+18
–10
–3
µA max
µA max
V max
V min
µA max
% FS/% V max
Reference Bias Current
Power Supply
Sensitivity
I15
PSSIFS+
PSSIFS–
V+ = +4.5 V to +18 V
V– = –4.5 V to –18 V
0.01
0.01
0.01
I
REF = 1.0 mA
Power Supply Current
Power Dissipation
I+
VS = 15 V
IREF ≤ 2.0 mA
VS = 15 V
IREF ≤ 2.0 mA
3.8
–7.8
174
3.8
–7.8
174
3.8
–7.8
174
mA max
µA max
mW max
PD
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–