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DAC0854CIWM PDF预览

DAC0854CIWM

更新时间： 2024-02-27 22:34:17
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器光电二极管
页数 文件大小 规格书
14页 271K
描述
8-Bit Voltage-Output

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DAC0854CIWM 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.84
最大模拟输出电压：2.8 V最小模拟输出电压：0.3 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：R-GDIP-T20
长度：24.51 mm最大线性误差 (EL)：0.3906%
位数：8功能数量：4
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
座面最大高度：5.08 mm标称安定时间 (tstl)：2.7 µs
标称供电电压：5 V表面贴装：NO
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

DAC0854CIWM 数据手册

 浏览型号DAC0854CIWM的Datasheet PDF文件第7页浏览型号DAC0854CIWM的Datasheet PDF文件第8页浏览型号DAC0854CIWM的Datasheet PDF文件第9页浏览型号DAC0854CIWM的Datasheet PDF文件第11页浏览型号DAC0854CIWM的Datasheet PDF文件第12页浏览型号DAC0854CIWM的Datasheet PDF文件第13页 
Digital Interface  
The DAC0854 has two interface modes: a WRITE mode  
and a READ mode. The WRITE mode is used to convert an  
8-bit digital input word into a voltage. The READ mode is  
used to read back the digital data that was sent to one or all  
of the DACs. These modes are selected by the appropriate  
setting of the RD/WR bit, which is part of the instruction  
byte. The instruction byte precedes the data byte at the DI  
pin. In both modes, a high level on the Start Bit (SB) alerts  
the DAC to respond to the remainder of the input stream.  
Table I lists the instruction set for the WRITE mode when  
writing to only a single DAC, and Table II lists the instruction  
set for a global write. The DACs are always written to LSB  
first. All DACs will be written to if the global bit (G) is high;  
DAC 1 is written to first, then DACs 2, 3 and 4 (in that order).  
If the update bit is high, then the DAC output will be updated  
on the rising edge of CS; otherwise, the new data byte will  
be placed only in the input register. Chip Select (CS) must  
remain low for at least one clock cycle after the last data bit  
has been entered. (See Figures 1 and 2 )  
TABLE I. WRITE Mode Instruction Set (Writing to a Single DAC)  
SB  
RD/WR  
G
U
A1  
A0  
Description  
Ý
Ý
Ý
Ý
Ý
Ý
Bit 6  
Bit  
1
Bit  
2
Bit  
3
Bit  
4
Bit  
5
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write DAC 1, no update of DAC outputs  
Write DAC 2, no update of DAC outputs  
Write DAC 3, no update of DAC outputs  
Write DAC 4, no update of DAC outputs  
Write DAC 1, update DAC 1 on CS rising edge  
Write DAC 2, update DAC 2 on CS rising edge  
Write DAC 3, update DAC 3 on CS rising edge  
Write DAC 4, update DAC 4 on CS rising edge  
0
0
0
0
0
0
0
TABLE II. WRITE Mode Instruction Set (Writing to all DACs)  
SB  
RD/WR  
G
U
Description  
Ý
Ý
Ý
Ý
Bit 4  
Bit  
1
Bit  
2
Bit  
3
1
0
1
1
0
1
Write all DACs, no update of outputs  
1
0
Write all DACs, update all outputs on CS rising edge  
10  
1...7891011121314

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