DAC-1212
12-Bit, 125MSPS, Low-Power D/A Converters
Ground Planes
Board Assembly Considerations
Precision converters provide high accuracyover temperature extremes, but some PC board
assemblyprecautions are necessary. Changes in DC parameters can be expected with Pb-free
SF ꢁPXꢁQSP ꢁMFTꢁPSꢁXBWFꢁTPMEFSꢁPOꢁNVMUJMBZFSꢁ'3ꢐꢁ1$ꢁCPBSETꢈꢁ1SFDBVUJPOTꢁTIPVMEꢁCFꢁUBLFOꢁUPꢁ
BWPJEꢁFYDFTTJWFꢁIFBUꢁPSꢁFYUFOEFEꢁFYQPTVSFꢁUPꢁIJHIꢁSF ꢁPXꢁPSꢁXBWFꢁTPMEFSꢁUFNQFSBUVSFTꢂꢁUIJTꢁNBZꢁ
reduce device initial accuracy.
If separate DGND and AGND planes are used, then all of the digital functions of the device and
the corresponding components should be located over the DGND plane and terminated to the
DGND plane.The same is true for the analog components and the AGND. Ifproper grounding
practices are implemented the converter will function properly with a single common ground
plane.
PIN DESCRIPTIONS
Supply Bypassing
PIN
PIN NAME
BIT 1(MSB)
DESCRIPTION
To minimize power supply noise, 0.1uF capacitors should be placed as close as possible to the
converter’s power supply pins, AVDD and DVDD. Be assured that capacitors are bypassed to their
proper AGND or DGND planes.
1 -12 through B12 (LSB) Digital Data input bits. B1 (MSB), B12 (LSB).
13-14
NC
No Connection. For noise rejection may be tied to AGND.
Control pin to power-down the DAC. Sleep = HI, On =
Humidity Susceptibility
15
SHTDWN
REFSEL
REFI/O
LO. Internal 20µA active pull-down current.
Plastic mold compounds that are used to house ICs can absorb moisture.When these devices are
exposedto humiditythe plastic package can undergo slight changes that can applypressure
to the internal die. Stresses placedon a precision data converters can cause changes in its
QFSGPSNBODFꢀJOꢀUIFꢀPSEFSꢀPGꢀꢁꢍꢍQQNꢌꢀ5IFꢀGVMMZꢀIFSNFUJDꢀQBDLBHFꢀP ꢀFSFEꢀGPSꢀUIFꢀo2-ꢀBOEꢀꢆꢅꢅꢇꢀ
WFSTJPOTꢀBSFꢀOPUꢀB ꢀFDUFEꢀCZꢀIVNJEJUZꢈꢀBOEꢀBSFꢀUIFSFGPSFꢀNPSFꢀTUBCMFꢀJOꢀFOWJSPONFOUTꢀXIFSFꢀ
humidity is a concern.
Connect to AGND to enable internal 1.2V reference. Con-
16
nect to AVDD to disable internal reference.
Reference voltage output when using internal 1.2V refer-
ence Input pin when supplying external reference.
Full Scale current adjustment (gain). Use resistor to AGND
to set current
17
18
19
20
GAINADJ
COMP
AGND
(see technical notes).
External capacitor to AGND helps to reduce bandwidth.
Board Mounting Considerations
Analog Ground
Complimentary output current. Full scale is attained when
digital inputs are at all 0's.
For applications requiring the highest accuracy, attention should be paid to the board mounting
location of SE and SM devices.These models use a plasticTSSOP package that could subject
the die to mild stresses when the printed circuit board is cooled or heated. Placing the device
in areas subject toslight twisting maycause die stresses and consequently degradation in
the accuracy of the converter. It is preferred that the device be placedin the center of the PCB
PSꢁOFBSꢁUIFꢁFEHFꢁPGꢁUIFꢁTIPSUFTUꢁTJEFꢁXIFSFꢁTUSFTTFTꢁEVFꢁUPꢁ ꢁFYJOHꢁBSFꢁSFEVDFEꢈꢁ.PVOUJOHꢁ
UIFꢁEFWJDFꢁJOꢁBꢁꢁDVUPVUꢁBMTPꢁNJOJNJ[FTꢁ ꢁFYꢈꢁ.PVOUJOHꢁUIFꢁEFWJDFꢁPOꢁBOꢁFYUSFNFMZꢁꢁUIJOꢁ1$#ꢁPSꢁ
ꢁFYQSJOUꢁXJMMꢁJODSFBTFꢁUIFꢁQPUFOUJBMꢁGPSꢁMPTTꢁPGꢁBDDVSBDZꢁEVFꢁUPꢁTUSFTTꢈꢁ5IFꢁ$-$$ꢁQBDLBHFꢁP ꢁFSFEꢁ
for -QL and /883 devices eliminates the potential for die stress.
21
IOUTB
True output current. Full scale is attained when digital
inputs are at all 1's.
22
23
24
25
26
27
IOUTA
NC
AVDD
AGND
DGND
DVDD
Do notconnect. Internal resistive connection to AGND.
Supply for analog circuitry (typically +3V to +5V).
Analog Ground
Digital Ground
Supply for digital circuitry (typically +3V to +5V).
Rising edge of clock latchesdata into input registers
thereby updating converter.
28
CLK
GLOSSARY OF SPECIFICATIONS
DIFFERENTIAL LINEARITY ERROR:The maximum deviation of anyquantum (LSB change) in the transfer function of a data converter from itsideal size of FSR/2n.
DIFFERENTIAL LINEARITY TEMPCO:5IFꢀDIBOHFꢀJOꢀEJ ꢀFSFOUJBMꢀMJOFBSJUZꢀFSSPSꢀXJUIꢀUFNQFSBUVSFꢀGPSꢀBꢀEBUBꢀDPOWFSUFSꢈꢀFYQSFTTFEꢀJOꢀQQNꢆ¡$ꢀPGꢀ'43ꢀꢉ'VMMꢀ4DBMFꢀ3BOHFꢊꢌ
GAIN ERROR:5IFꢀEJ ꢀFSFODFꢀJOꢀTMPQFꢀCFUXFFOꢀUIFꢀBDUVBMꢀBOEꢀJEFBMꢀUSBOTGFSꢀGVODUJPOTꢀGPSꢀBꢀEBUBꢀDPOWFSUFSꢀPSꢀPUIFSꢀDJSDVJUꢌꢀ*UꢀJTꢀFYQSFTTFEꢀBTꢀBꢀQFSDFOUꢀPGꢀBOBMPHꢀNBHOJUVEFꢌ
GAIN TEMPCO:The change in gain (or scale factor) with temperature for a data converter or other circuit, generally expressedin ppm/°C.
INTEGRAL LINEARITY ERROR:ꢀ5IFꢀNBYJNVNꢀEFWJBUJPOꢀPGꢀBꢀEBUBꢀDPOWFSUFSꢀUSBOTGFSꢀGVODUJPOꢀGSPNꢀUIFꢀJEFBMꢀTUSBJHIUꢀMJOFꢀXJUIꢀP ꢀTFUꢀBOEꢀHBJOꢀFSSPSTꢀ[FSPFEꢌꢀ*UꢀJTꢀHFOFSBMMZꢀFYQSFTTFEꢀJOꢀ-4#hTꢀPSꢀJOꢀ
percent of FSR.
INTERNAL REFERENCE VOLTAGE DRIFT:The maximum deviation from the measured value at room temperature as compared with the value measured at eitherTmin orTmax.
OUTPUT COMPLIANCE RANGE:The allowable MaximumVoltage at the output of a D/A.
OFFSET ERROR:The deviation from the ideal at analog zero output
OFFSET DRIFT: The change with temperature ofanalog zero for a data converter operating in the bipolar mode. Itis generally expressed in ppm/°C of FSR.
108&3ꢀ4611-:ꢀ3&+&$5*0/ꢀ3"5*0ꢀŷ1433Ÿ: 5IFꢁPVUQVUꢁDIBOHFꢁJOꢁBꢁEBUBꢁDPOWFSUFSꢁDBVTFEꢁCZꢁBꢁDIBOHFꢁJOꢁQPXFSꢁTVQQMZꢁWPMUBHFꢈꢁ1PXFSꢁTVQQMZꢁTFOTJUJWJUZꢁJTꢁHFOFSBMMZꢁTQFDJ ꢁFEꢁJOꢁꢏꢎ7ꢁPSꢁJOꢁꢏꢎꢏꢁ
supply change.
REFERENCE INPUT MULTIPLYING BANDWIDTH: The -3dB reduction in the output when applying a sinusoidal voltage to the external reference (digital inputs are set to all 1s).The frequency is
increaseduntil the amplitude of the output waveform is -3dB of its original value.
SETTLINGTIME: 5IFꢁUJNFꢁFMBQTFEꢁGSPNꢁUIFꢁBQQMJDBUJPOꢁPGꢁBꢁGVMMꢁTDBMFꢁTUFQꢁJOQVUꢁUPꢁꢁBꢁDJSDVJUꢁUPꢁUIFꢁUJNFꢁXIFOꢁUIFꢁPVUQVUꢁIBTꢁFOUFSFEꢁBOEꢁSFNBJOFEꢁXJUIJOꢁBꢁTQFDJ ꢁFEꢁFSSPSꢁCBOEꢁBSPVOEꢁJUTꢁ ꢁOBMꢁ
WBMVFꢈꢁ5IJTꢁUFSNꢁJTꢁBOꢁJNQPSUBOUꢁTQFDJ ꢁDBUJPOꢁGPSꢁPQFSBUJPOBMꢁBNQMJ ꢁFSTꢂꢁBOBMPHꢁNVMUJQMFYFSTꢂꢁBOEꢁ%ꢎ"ꢁDPOWFSUFSTꢈ
TOTAL HARMONIC DISTORTION:ꢁ5IFꢁSBUJPꢁPGꢁUIFꢁSNTꢁꢁTVNꢁPGꢁUIFꢁ ꢁSTUꢁꢅꢁIBSNPOJDTꢁUPꢁUIFꢁSNTꢁPGꢁUIFꢁGVOEBNFOUBMꢁTJHOBMꢂꢁVTVBMMZꢁFYQSFTTFEꢁJOꢁE#
GLITCH AREA: The transientappearing at the output when the input switches from one code to another.Typically the worst case is found atthe MSB code transition. It is measured as the area
VOEFSꢁUIFꢁPWFSTIPPUꢁQPSUJPOꢁPGꢁUIFꢁDVSWFꢁBOEꢁJTꢁFYQSFTTFEꢁBTꢁBꢁ7PMUꢀ5JNFꢁTQFDJ ꢁDBUJPOꢈ
SPURIOUS FREE DYNAMIC RANGE (SFDR): The largest harmonic, spurious frequency or noise component in a signal FFT. It is expressed in db with respect to the fundamental frequency.
%"5&-ꢀꢁ*ODꢂꢁꢃꢃꢁ$BCPUꢁ#PVMFWBSEꢀꢁ.BOT ꢁFMEꢀꢁ."ꢁꢄꢅꢄꢆꢇꢁ64"ꢁ tꢁ 5FMꢈꢁꢉꢊꢄꢇꢋꢌꢍꢆꢎꢊꢏꢌꢐꢁ tꢁ XXXꢂEBUFMꢂDPNꢁ tꢁ FꢎNBJMꢈꢁIFMQ!EBUFMꢂDPN
30 October 2015 MDA_DAC-1212.C01.D1 Page4 of 7
5秒后页面跳转
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
PCF8574资料解读：主要参数分析、引脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
