DAC-1212
12-Bit, 125MSPS, Low-Power D/A Converters
Voltage Reference
TIMING CHARACTERISTICS
TEST CONDITION MIN.
TYP.
1.5
1.3
MAX.
UNITS
ns
ns
ns
ns
Data SetupTime7 (tsu)
Data HoldTime7 (thld)
Propagation DelayTime7 (tpd)
Clock (CLK) PulseWidth HI7
Clock (CLK) PulseWidth LO7
POWER REQUIREMENTS
Power Supply Ranges
AVDD3
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over the full temperature range. It is recommended that a bypass capacitor be placed as
close as possible to the REFI/O pin, connected to AGND.The REFSEL (pin 16) selects whether
an internal or external reference is used..The internal reference can be selected if pin 16 is
tied low (AGND). If an external reference is desired, then pin 16 should be tied high (AVDD)
and the external reference driven into REFI/O, pin 17.The full scale output current of the
converter is a function of both the reference voltage and the value of RSET. IOUT should be
within the 2mA to 20mA range. Performance may degrade at 2mA FS Iout.
2.3
4
4
ns
2.7
2.7
5.0
5.0
5.5
5.5
Volts
Volts
DVDD3
If the internal reference is used, the voltage at GAINADJ (VGAINADJ) will equal approxi-
mately 1.16V (pin 18). If an external reference is used, the voltage at GAINADJ will equal
the external reference. IOUT Full Scale can be calculated as:
Power Supply Currents
AVDD4 (3V to 5V)
AVDD4 (3V to 5V)
DVDD4
IOUT = 20mA
IOUT = 2mA
5V
24
6
12
6
mA
mA
mA
IOUT FS = (VGAINADJ/RSET)x 32
DVDD4
3V
mA
AVDD Shut-Down Mode
Power Dissipation
3V or 5V
2.7
80
150
32
76
mA
If the full scale output current is set to 20mA by using the internal voltage reference (1.16V)
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as follows:
5V, IOUT = 2mA4
5V, IOUT = 20mA6
3V, IOUT = 2mA4
3V, IOUT = 20mA6
mW
mW
mW
mW
INPUT CODE / IOUT
INPUT CODE (B1 - B12)
1111 1111 1111
1000 0000 0000
0000 0000 0000
IOUTA (mA)
IOUTB (mA)
Power Supply Rejection Ratio
-0.2
+0.2
% FSR/V
20
10
0
0
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10
20
Ideal ratio = 31.969.
3. For optimal performance, when operating with supply voltages below 3V IOUT should be less than
12mA.
4. fclock = 100MHz, fout = 39MHz.
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6. fclock = 50MHz, fout= 2MHz
7. See Figure 4
Output Current
IOUTA and IOUTB provide complementary output current.The sum of IOUTA and IOUTB is
always equal to the full scale output current minus one LSB. For single-ended applications,
a load resistor can be used to convert the outputcurrentto a voltage. It is recommended
that the unused output be terminated with an equivalent value
resistance or con-
nected to AGND.The voltage developed at the output must notexceed the output voltage
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desired outputvoltage:
TECHNICAL NOTES
Theory of Operation
VOUT = IOUT X RLOAD
The DAC-1212 is an 12-bit, 20mA current output, CMOS, digital to analog converter.The
maximum conversion rate is 125MSPS with an operating power supply range of +3V to +5V.
The design topology incorporates segmented currentsource circuitry thatreduces transient
glitches.The upper bits are divided into major current sources of equivalent current.The re-
maining lower bits are comprised of binary weighted current sources. In the situation where
an input waveform tothe converter is rampedthrough all the codes from 0 to4095, when
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lower bits will again count up until the next major current source turns on and the lower bits
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overall glitch of the converter thereby improving output settling times and transient spikes.
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harmonic rejection.The SFDR measurements in this data sheet were attained using a 1:1
transformer on the output of the DAC (see Figure 2).With the center tap grounded, the
output swingof pins 21 and22 will be biased at zero volts. It is importanttonote here that
the negative voltage outputcompliance range limit is -300mV, imposing a maximum of
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in a 500mV signal at the output of the transformer if the full scale output current of the
DAC is set to 20mA.
Digital Inputs / Termination
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voltage to 3V will reduce the logic threshold level and thereby provideTTLcompatible
inputs.The internal CMOSregister is updated on the rising edge of the clock.To minimize
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possible.
Figure 2
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30 October 2015 MDA_DAC-1212.C01.D1 Page3 of 7
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