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D3V3F8U9LP3810 PDF预览

D3V3F8U9LP3810

更新时间: 2023-12-06 20:11:21
品牌 Logo 应用领域
美台 - DIODES 电视
页数 文件大小 规格书
5页 390K
描述
8 CHANNEL LOW CAPACITANCE TVS DIODE ARRAY

D3V3F8U9LP3810 数据手册

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D3V3F8U9LP3810  
Maximum Ratings (@TA = +25°C, unless otherwise specified.)  
Characteristic  
Peak Pulse Current, per IEC 61000-4-5  
Peak Pulse Power, per IEC 61000-4-5  
Symbol  
Value  
Unit  
Conditions  
I/O to VSS, 8/20µs  
I/O to VSS, 8/20µs  
5
A
IPP  
PPP  
32  
W
ESD Protection Contact Discharge, per IEC 61000-4-2  
ESD Protection Air Discharge, per IEC 61000-4-2  
Operating Temperature  
±12  
±12  
kV  
kV  
°C  
°C  
VESD_CONTACT  
VESD_AIR  
TOP  
I/O to VSS  
I/O to VSS  
-55 to +85  
-55 to +150  
Storage Temperature  
TSTG  
Thermal Characteristics  
Characteristic  
Power Dissipation Typical (Note 5)  
Symbol  
PD  
R  
Value  
350  
Unit  
mW  
Thermal Resistance, Junction to Ambient Typical (Note 5)  
360  
°C/W  
JA  
Electrical Characteristics (@TA = +25°C, unless otherwise specified.)  
Characteristic  
Reverse Working Voltage  
Symbol  
VRWM  
IR  
Min  
Typ  
Max  
Unit  
V
Test Conditions  
3.3  
1.0  
IR=1mA, I/O to VSS  
Reverse Current  
μA  
V
VR = 3.3V, I/O to VSS  
IR = 1mA, I/O to VSS  
IF = -15mA, I/O to VSS  
I/O to VSS  
Reverse Breakdown Voltage  
Forward Clamping Voltage  
Holding Reverse Voltage  
Holding Reverse Current  
Clamping Voltage (Note 6)  
Clamping Voltage (Note 6)  
Dynamic Reverse Resistance  
Dynamic Forward Resistance  
Channel Input Capacitance  
5.5  
-1.0  
7.0  
-0.85  
1.19  
90  
VBR  
V
VF  
V
VHOLD  
IHOLD  
VC  
mA  
V
I/O to VSS  
5
TLP, 16A, tp = 100ns, I/O to VSS  
TLP, -16A, tp = 100ns, I/O to VSS  
5
V
VC  
0.25  
0.2  
0.55  
RDIF-R  
RDIF-F  
CI/O  
TLP, 10A, tp = 100ns, I/O to VSS  
TLP, 10A, tp = 100ns, VSS to I/O  
VI/O = 0V, VSS = 0V, f = 1MHz  
pF  
Notes:  
5. Device mounted on FR-4 PCB pad layout (2oz copper) as shown on Diodes Incorporated’s suggested pad layout, which can be found on our website at  
http://www.diodes.com/package-outlines.html.  
6. Clamping voltage value is based on a TLP model. TLP conditions: Z0=50, tp = 100ns, averaging window; t1=70ns to t2=90ns.  
2 of 5  
www.diodes.com  
October 2017  
© Diodes Incorporated  
D3V3F8U9LP3810  
Document number: DS39456 Rev. 1 2  

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