DS1672
AC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX UNITS NOTES
Fast mode
fSCL
100
400
100
SCL Clock
kHz
Frequency
Standard mode
Bus Free Time
Between a STOP and
START Condition
Hold Time
Fast mode
tBUF
1.3
4.7
0.6
µs
Standard mode
Fast mode
tHD:STA
6
(Repeated) START
Condition
µs
µs
µs
Standard mode
4.0
1.3
4.7
Fast mode
Standard mode
LOW Period of SCL
tLOW
Clock
Fast mode
tHIGH
0.6
4.0
0.6
4.7
HIGH Period of SCL
Clock
Standard mode
Setup Time for a
Repeated START
Condition
Fast mode
tSU:STA
µs
Standard mode
Fast mode
tHD:DAT
0
0.9
Data Hold Time
7, 8
9
µs
ns
ns
ns
Standard mode
0
100
250
Fast mode
Standard mode
Data Setup Time
tSU:DAT
Rise Time of Both
SDA and SCL
Signals
Fall Time of Both
SDA and SCL
Signals
Fast mode
20 + 0.1CB
300
1000
300
tR
10
10
Standard mode
Fast mode
tF
20 + 0.1CB
Standard mode
300
Fast mode
tSU:STO
0.6
4.0
Setup Time for STOP
Condition
µs
Standard mode
Capacitive Load for
Each Bus Line
I/O Capacitance
CB
400
pF
pF
10
CI/O
10
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIHMIN of the SCL signal) in
order to bridge the undefined region of the falling edge of SCL.
Note 8:The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 10: CB–Total capacitance of one bus line in pF.
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