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CYW181-51SX PDF预览

CYW181-51SX

更新时间： 2024-02-09 02:49:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
9页 190K
描述
Peak-Reducing EMI Solution

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CYW181-51SX 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：0.150 INCH, LEAD FREE, MS-012, SOIC-8针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N其他特性：ALSO OPERATES AT 5V SUPPLY
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.889 mm湿度敏感等级：1
端子数量：8最高工作温度：70 °C
最低工作温度：最大输出时钟频率：75 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260主时钟/晶体标称频率：75 MHz
认证状态：Not Qualified座面最大高度：1.727 mm
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.8985 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

CYW181-51SX 数据手册

 浏览型号CYW181-51SX的Datasheet PDF文件第1页浏览型号CYW181-51SX的Datasheet PDF文件第2页浏览型号CYW181-51SX的Datasheet PDF文件第4页浏览型号CYW181-51SX的Datasheet PDF文件第5页浏览型号CYW181-51SX的Datasheet PDF文件第6页浏览型号CYW181-51SX的Datasheet PDF文件第7页 
W181  
Because the modulating frequency is typically 1000 times  
slower than the fundamental clock, the spread spectrum  
process has little impact on system performance.  
Using frequency select bits (FS1:2 pins), the frequency range  
can be set. Spreading percentage is set to be 1.25% or 3.75%  
(see Table 1).  
A larger spreading percentage improves EMI reduction.  
However, large spread percentages may either exceed  
system maximum frequency ratings or lower the average  
frequency to a point where performance is affected. For these  
reasons, spreading percentages between 0.5% and 2.5% are  
most common.  
Frequency Selection With SSFTG  
In Spread Spectrum Frequency Timing Generation, EMI  
reduction depends on the shape, modulation percentage, and  
frequency of the modulating waveform. While the shape and  
frequency of the modulating waveform are fixed for a given  
frequency, the modulation percentage may be varied.  
V
DD  
Clock Input  
CLKOUT  
(EMI suppressed)  
Freq.  
Divider  
Q
Phase  
Charge  
Pump  
Post  
Reference Input  
VCO  
Σ
Detector  
Dividers  
Modulating  
Waveform  
Feedback  
Divider  
P
PLL  
GND  
Figure 1. Functional Block Diagram  
The output clock is modulated with a waveform depicted in  
Figure 3. This waveform, as discussed in “Spread Spectrum  
Clock Generation for the Reduction of Radiated Emissions” by  
Bush, Fessler, and Hardin produces the maximum reduction  
in the amplitude of radiated electromagnetic emissions.  
Figure 3 details the Cypress spreading pattern. Cypress does  
offer options with more spread and greater EMI reduction.  
Contact your local Sales representative for details on these  
devices.  
Spread Spectrum Frequency Timing  
Generation  
The device generates a clock that is frequency modulated in  
order to increase the bandwidth that it occupies. By increasing  
the bandwidth of the fundamental and its harmonics, the ampli-  
tudes of the radiated electromagnetic emissions are reduced.  
This effect is depicted in Figure 2.  
As shown in Figure 2, a harmonic of a modulated clock has a  
much lower amplitude than that of an unmodulated signal. The  
reduction in amplitude is dependent on the harmonic number  
and the frequency deviation or spread. The equation for the  
reduction is:  
dB = 6.5 + 9*log10(P) + 9*log10(F)  
where P is the percentage of deviation and F is the frequency  
in MHz where the reduction is measured.  
Document #: 38-07152 Rev. *D  
Page 3 of 9  
1234567...9

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