W181
Pin Definitions
Pin No.
Pin No.
Pin
Pin Name
(SOIC)
(TSSOP)(-01) Type
Pin Description
CLKOUT
5
8
2
O
I
Output Modulated Frequency: Frequency modulated copy of the
unmodulated input clock (SSON# asserted).
CLKIN or X1
1
Crystal Connection or External Reference Frequency Input: This pin
has dual functions. It may either be connected to an external crystal, or
to an external reference clock.
NC or X2
SSON#
2
3
I
I
Crystal Connection: If using an external reference, this pin must be left
unconnected.
8(02/03/52/53)
--
Spread Spectrum Control (Active LOW): Asserting this signal (active
LOW) turns the internal modulation waveform on. This pin has an internal
pull-down resistor.
FS1:2
SS%
7, 8 (01/51)
4
12, 1
6
I
I
Frequency Selection Bit(s) 1 and 2: These pins select the frequency
range of operation. Refer to Table 2. These pins have internal pull-up
resistors.
Modulation Width Selection: When Spread Spectrum feature is turned
on, this pin is used to select the amount of variation and peak EMI
reduction that is desired on the output signal. This pin has an internal
pull-up resistor.
VDD
GND
6
3
10
4
P
G
Power Connection: Connected to 3.3V or 5V power supply.
Ground Connection: Connect all ground pins to the common system
ground plane.
NC
5, 7, 9, 11, 13, NC No Connection
14
Key Specifications
Overview
Supply Voltages: .........................................VDD = 3.3V ± 5%
The W181 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer
techniques. By frequency modulating the output with a
low-frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The
Simplified Block Diagram on page 1 shows a simple imple-
mentation.
.................................................................or VDD = 5V ± 10%
Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz
Crystal Reference Range.................. 28 MHz ≤ Fin ≤ 40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ................... 1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Table 1. Modulation Width Selection
SS% W181-01, 02, 03 Output W181-51, 52, 53 Output
Functional Description
0
–1.25%
±0.625
(Down Spread)
(Center Spread)
The W181 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W181 the output
frequency is equal to the input frequency.) The unique feature
of the Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a
predetermined frequency band.
1
–3.75%
±1.875%
(Down Spread)
(Center Spread)
Table 2. Frequency Range Selection
W181 Option#
-02, 52
-01, 51
(MHz)
-03, 53
(MHz)
N/A
FS2 FS1
(MHz)
0
0
1
1
0
1
0
1
28 ≤ FIN ≤ 38 28 ≤ FIN ≤ 38
38 ≤ FIN ≤ 48 38 ≤ FIN ≤ 48
46 ≤ FIN ≤ 60
58 ≤ FIN ≤ 75
N/A
46 ≤ FIN ≤ 60
58 ≤ FIN ≤ 75
N/A
N/A
Document #: 38-07152 Rev. *D
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