Datasheet > CYP15G0403DXB_11

CYP15G0403DXB_11

更新时间： 2022-10-24 17:20:53

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
48页	592K
描述
Independent Clock Quad HOTLink II Transceiver Single 3.3V supply

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数据手册

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CYP15G0403DXB_11 数据手册

CYP15G0403DXB

TXLB[A..D] are Internal Serial Loopback Signals

Receive Path Block Diagram

= Internal Signal

RESET

TRST

JTAG

TMS

TCLK

TDI

SPDSELA

Boundary

Scan

RXPLLPDA

SDASELA[1:0]

Controller

TDO

LFIA

Receive

Signal

LPENA

INSELA

Monitor

INA1+

INA1–

RXDA[7:0]

INA2+

INA2–

Clock &

Data

Recovery

PLL

TXLBA

RXSTA[2:0]

ULCA

SPDSELB

RXPLLPDB

SDASELB[1:0]

RXCLKA+

RXCLKA–

Clock

Select

2

Receive

Signal

Monitor

LPENB

INSELB

LFIB

INB1+

INB1–

RXDB[7:0]

Clock &

Data

Recovery

PLL

INB2+

INB2–

TXLBB

RXSTB[2:0]

ULCB

SPDSELC

Clock

Select

RXCLKB+

RXCLKB–

RXPLLPDC

SDASELC[1:0]

2

LPENC

INSELC

Receive

Signal

Monitor

LFIC

INC1+

INC1–

RXDC[7:0]

INC2+

INC2–

Clock &

Data

Recovery

PLL

TXLBC

RXSTC[2:0]

ULCC

SPDSELD

RXPLLPDD

SDASELD[1:0]

Clock

Select

RXCLKC+

RXCLKC–

2

LPEND

INSELD

Receive

Signal

Monitor

LFID

IND1+

IND1–

RXDD[7:0]

IND2+

IND2–

Clock &

Data

Recovery

PLL

TXLBD

RXSTD[2:0]

ULCD

Clock

Select

RXCLKD+

RXCLKD–

LDTDEN

2

RFMODE[A..D][1:0]

RFEN[A..D]

FRAMCHAR[A..D]

DECMODE[A..D]

RXBIST[A..D]

RXCKSEL[A..D]

DECBYP[A..D]

RXRATE[A..D]

Document #: 38-02065 Rev. *I

Page 6 of 48

1...3 4 567 8 9...48

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