Datasheet > CYP15G0403DXB_11

CYP15G0403DXB_11

更新时间： 2022-10-24 17:20:53

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
48页	592K
描述
Independent Clock Quad HOTLink II Transceiver Single 3.3V supply

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数据手册

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CYP15G0403DXB_11 数据手册

CYP15G0403DXB

TXLB[A..D] are Internal Serial Loopback Signals

Transmit Path Block Diagram

= Internal Signal

REFCLKA+

Bit-Rate Clock

OEA[2..1]

REFCLKA–

TXRATEA

TrTarannssmmiittPPLLLL

CClolocckkMMuultilptliiperlieAr

Character-Rate Clock A

PABRSTA

SPDSELA

TXCLKOA

ENCBYPA

TXERRA

TXCLKA

OEA[2..1]

TXBIST

TXCKSELA

OUTA1+

OUTA1–

TXDA[7:0]

OUTA2+

OUTA2–

TXCTA[1:0]

TXLBA

REFCLKB+

REFCLKB–

Bit-Rate Clock

OEB[2..1]

Transmit PLL

Clock Multiplier B

TXRATEB

SPDSELB

TXCLKOB

ENCBYPB

Character-Rate Clock B

PABRSTB

TXERRB

TXCLKB

TXBIST

OEB[2..1]

TXCKSELB

OUTB1+

OUTB1–

TXDB[7:0]

OUTB2+

OUTB2–

TXCTB[1:0]

TXLBB

REFCLKC+

REFCLKC–

Bit-Rate Clock

OEC[2..1]

Transmit PLL

Clock Multiplier C

TXRATEC

SPDSELC

TXCLKOC

ENCBYPC

Character-Rate Clock C

PABRSTC

TXERRC

TXCLKC

OEC[2..1]

TXBIST

TXCKSELC

OUTC1+

OUTC1–

TXDC[7:0]

OUTC2+

OUTC2–

TXCTC[1:0]

TXLBC

REFCLKD+

REFCLKD–

Bit-Rate Clock

OED[2..1]

Transmit PLL

Clock Multiplier D

TXRATED

SPDSELD

TXCLKOD

TXERRD

ENCBYPD

OED[2..1]

Character-Rate Clock D

PABRSTD

TXBISTD

TXCLKD

TXCKSELD

OUTD1+

OUTD1–

TXDD[7:0]

OUTD2+

OUTD2–

TXCTD[1:0]

TXLBD

Document #: 38-02065 Rev. *I

Page 5 of 48

1 2 3 456 7 8...48

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