CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Figure 1. HOTLink II™ System Connections
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10
Serial Links
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10
Serial Links
Independent
CYP(V)(W)15G0403DXB
Independent
CYP(V)(W)15G0403DXB
10
10
Serial Links
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Backplane or
Cabled
Connections
Serial Links
The receive (RX) section of the CYP(V)(W)15G0403DXB
Quad HOTLink II consists of four independent byte-wide
channels. Each channel accepts a serial bit-stream from one
of two PECL-compatible differential line receivers, and using
a completely integrated Clock and Data Recovery PLL,
recovers the timing information necessary for data recon-
struction. Each recovered bit-stream is deserialized and
framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are then
written to an internal Elasticity Buffer, and presented to the
destination host system.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path with a
local reference clock, the receive interface may also be
configured to present data relative to a recovered clock or to a
local reference clock.
Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
each transmit and receive section, and across the intercon-
necting links.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
The CYP(V)(W)15G0403DXB is ideal for port applications
where different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-protocol routers, aggregation equipment, and switches.
Document #: 38-02065 Rev. *F
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