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CYP15G0402DXB-BGXI

更新时间： 2024-01-15 16:30:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
29页	615K
描述
Quad HOTLink II⑩ SERDES

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技术参数
数据手册

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CYP15G0402DXB-BGXI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.92	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA256,20X20,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	225
电源：	1.5,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.745 mm	子类别：	Other Telecom ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BICMOS	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	27 mm	Base Number Matches：	1

CYP15G0402DXB-BGXI 数据手册

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CYP15G0402DXB

CYV15G0402DXB

second-generation

HOTLink

device,

the

The parallel input interface may be configured for numerous

forms of clocking to provide the high flexibility in system archi-

tecture.

Each transmit and receive channel contains an independent

BIST pattern generator and checker. This BIST hardware

allows at-speed testing of the interface data path.

HOTLink II devices are ideal for a variety of applications where

parallel interfaces can be replaced with high-speed,

point-to-point serial links. Some applications include intercon-

necting backplanes on switches, routers, servers and video

transmission systems.

The CYV15G0402DXB is verified by testing to be compliant to

all the pathological test patterns documented in SMPTE

EG34-1999, for both the SMPTE 259M and 292M signaling

rates. The tests ensure that the receiver recovers data with no

errors for the following patterns:

CYP(V)15G0402DXB extends the HOTLink family to faster

data rates, while maintaining serial link compatibility (data,

command and BIST) with other HOTLink devices.The transmit

(TX) section of the CYP(V)15G0402DXB Quad HOTLink II

SERDES consists of four ten bit wide channels that accept a

preencoded character on every clock cycle. Transmission

characters are passed from the Transmit Input Register to a

Serializer. The serialized characters are output from a differ-

ential transmission line driver at a bit-rate of 10 or 20 times the

input reference clock.

The receive (RX) section of the CYP(V)15G0402DXB Quad

HOTLink II SERDES consists of four ten bit wide channels.

Each channel accepts

serial bit-stream from

PECL-compatible differential line receiver and, using a

completely integrated PLL Clock Synchronizer, recovers the

timing information necessary for data reconstruction. Each

recovered bit-stream is deserialized and framed into

characters. Recovered characters are then passed to the

receiver output register, along with a recovered character

clock.

1. Repetitions of 20 ones and 20 zeros.

2. Single burst of 44 ones or 44 zeros.

3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol-

lowed by 1 one.

CYP(V)15G0402DXB Transceiver Logic Block Diagram

x10

Phase

Align

Phase

Align

Phase

Align

Phase

Align

Framer

Buffer

Serializer

Deserializer

Serializer

Deserializer

Serializer

Deserializer

Document #: 38-02057 Rev. *G

Page 2 of 29

123 4 5 6 7...29

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与CYP15G0402DXB-BGXI相关器件

型号	品牌	描述	获取价格	数据表
CYP15G0402DX-BGC	CYPRESS	Quad HOTLinkII SERDES	获取价格
CYP15G0402DX-BGI	CYPRESS	Quad HOTLinkII SERDES	获取价格
CYP15G0403DXB	CYPRESS	Independent Clock Quad HOTLink II⑩ Transceive	获取价格
CYP15G0403DXB_07	CYPRESS	Independent Clock Quad HOTLink II⑩ Transceive	获取价格
CYP15G0403DXB_09	CYPRESS	Independent Clock Quad HOTLink II Transceiver	获取价格
CYP15G0403DXB_11	CYPRESS	Independent Clock Quad HOTLink II Transceiver Single 3.3V supply	获取价格

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