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CYIIFM1300AB-QDC PDF预览

CYIIFM1300AB-QDC

更新时间: 2024-02-16 02:45:42
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 传感器换能器图像传感器时钟
页数 文件大小 规格书
40页 1675K
描述
1.3 MP CMOS Image Sensor

CYIIFM1300AB-QDC 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5Is Samacsys:N
其他特性:ELECTRONIC SHUTTER, GLOBAL SHUTTER阵列类型:FULL FRAME
主体宽度:15.24 mm主体高度:2.25 mm
主体长度或直径:15.24 mm数据速率:40 Mbps
动态范围:64 dB帧速率:27 fps
水平像素:1280外壳:CERAMIC
主时钟:40 MHz安装特点:SURFACE MOUNT
最大工作电流:60 mA最高工作温度:65 °C
最低工作温度:光学格式:2/3 inch
输出接口类型:SPI INTERFACE输出范围:0.60-2.10V
输出类型:DIGITAL VOLTAGE封装形状/形式:SQUARE
像素大小:6.7X6.7 µm灵敏度(V / lx.s):8.4 V/lx.s
传感器/换能器类型:IMAGE SENSOR,CMOS最大供电电压:4.5 V
最小供电电压:3 V表面贴装:YES
端接类型:SOLDER垂直像素:1024
Base Number Matches:1

CYIIFM1300AB-QDC 数据手册

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IBIS5-B-1300 CYII5FM1300AB  
Architecture and Operation  
This section presents detailed information about the most important sensor blocks.  
Floor Plan  
Figure 1. Block Diagram of the IBIS5-B-1300 Image Sensor  
Sensor  
Imager core  
Reset  
C
Select  
Pixel  
Y-left  
Y-right  
Sample  
addressing  
addressing  
Column output  
Pixel core  
Sequencer  
Column amplifiers  
System clock  
40 MHz  
Output  
amplifier  
Analog multiplexer  
X-addressing  
External  
connection  
ADC  
Figure 1 shows the architecture of the IBIS5-B-1300 image  
sensor. It consists basically of a pixel array, one X- and two  
Y-addressing registers for the readout in X- and Y-direction,  
column amplifiers that correct for the fixed pattern noise, an  
analog multiplexer, and an analog output amplifier.  
Architecture  
The pixel architecture used in the IBIS5-B-1300 is a 4-transistor  
pixel as shown in Figure 2. Implement the pixel using the high fill  
factor technique as patented by Cypress (US patent No.  
6,225,670 and others). The 4T-pixel features a snapshot shutter  
but can also emulate the 3T-pixel by continuously closing  
sampling switch M2. Using M4 as a global sample transistor for  
all pixels enables the snapshot shutter mode. Due to this pixel  
architecture, integration during read out is not possible in  
synchronous shutter mode.  
Use the left Y-addressing register for readout operation. Use the  
right Y-addressing register for reset of pixel rows. In multiple  
slope synchronous shutter mode, the right Y-addressing register  
resets the whole pixel core with a lowered reset voltage. In rolling  
curtain shutter mode, use the right Y-addressing register for the  
reset pointer in single and double slope operation to reset one  
pixel row.  
Figure 2. Architecture of the 4T-pixel  
The on-chip sequencer generates most of the signals for the  
image core. Some basic signals (like start/stop integration, line  
and frame sync signals, and others.) are generated externally.  
reset  
M1  
A 10-bit ADC is implemented on chip but electrically isolated  
from the image core. You must route the analog pixel output to  
the analog ADC input on the outside.  
C
mux  
M4  
M3  
M2  
Pixel  
sample  
column  
output  
A description of the pixel architecture and the color filter array  
follows.  
Document #: 38-05710 Rev. *C  
Page 2 of 40  

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